PIC24FJ64GA004-E/ML Microchip Technology, PIC24FJ64GA004-E/ML Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ64GA004-E/ML
• Description: 16-bit Family, 16 MIPS, 64KB Flash, 8192 Bytes RAM, 35 I/O, NanoWatt 44 QFN 8x8x
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA004-E/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ64GA004 FAMILY
TABLE 2:
DS80470E-page 2
JTAG
LVD
Core
Core
Core
Core
A/D
A/D
A/D
I
UART
UART
UART
UART
UART
UART
Output
Compare
SPI
SPI
SPI
I/O
I/O
JTAG
RTCC
I
I
UART
I/O
UART
Note 1:
2
2
2
C
C
C
Module
Only those issues indicated in the last column apply to the current silicon revision.
Idle mode
Doze mode
BOR
RAM
SDA Line
State (I2C1)
Auto-Baud
Auto-Baud
Auto-Baud
Break
Character
Generation
Enhanced
Buffer mode
Enhanced
Buffer mode
Slave mode
IrDA
PPS
UERIF
Interrupt
SILICON ISSUE SUMMARY
Feature
®
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Persistent pull-up (RA3) when JTAG
disabled.
No LVD interrupt with low-voltage condition
at Reset.
Clock failure trap fails in Idle mode.
RAM read repeat on entering Doze mode.
POR and BOR flags both set on BOR.
RAM size implementation on some devices.
Unimplemented channels may be selected.
Missing midscale conversion code.
Device may not wake when convert on INT0
trigger is selected.
Line state may not be detected correctly.
Reception failures in High-Speed mode.
Erroneous baud rate calculations in
High-Speed mode.
Double receive interrupt with auto-baud
reception.
Insertion of spurious data with auto-baud
reception.
Auto-baud calculation errors causing
transmit or receive failures.
The UART module will not generate
back-to-back Break characters.
Single missed compare events under certain
conditions.
Some flag bits are set at incorrect times in
Enhanced Buffer mode.
Module in Slave mode may ignore SS pin
and receive data anyway.
No SPI interrupt in Enhanced Buffer mode
under certain conditions.
Spec change for V
OSCO/RA3 driven immediately following
POR.
Sync loss in ICSP™ mode.
Write errors to ALCFGRPT register.
In Slave mode, ACKSTAT bit state change.
Issues with write operations on I2CxSTAT.
IR baud clock only available during transmit.
Issues with digital signal priorities with RP12
and RP18.
No UERIF flag with multiple errors.
Issue Summary
OL
and V
OH
.
A3/A4
 2010 Microchip Technology Inc.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected Revisions
B4
X
X
B5
X
X
(1)
B8
X
X