PIC24HJ128GP504T-I/ML Microchip Technology, PIC24HJ128GP504T-I/ML Datasheet - Page 58
![16-bit MCU, 128KB Flash,CAN,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24HJ128GP504T-I/ML
Manufacturer Part Number
PIC24HJ128GP504T-I/ML
Description
16-bit MCU, 128KB Flash,CAN,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ128GP504T-I/ML
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (43K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24HJ128GP504T-I/MLTR
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- Current page: 58 of 368
- Download datasheet (5Mb)
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
EXAMPLE 5-2:
EXAMPLE 5-3:
DS70293E-page 58
; Set up NVMCON for row programming operations
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
; Perform the TBLWT instructions to write the latches
; 0th_program_word
; 1st_program_word
;
; 63rd_program_word
2nd_program_word
MOV
MOV
MOV
MOV
MOV
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
•
•
•
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x4001, W0
W0, NVMCON
#0x0000, W0
W0, TBLPAG
#0x6000, W0
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
#5
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
LOADING THE WRITE BUFFERS
INITIATING A PROGRAMMING SEQUENCE
;
; Initialize NVMCON
;
; Initialize PM Page Boundary SFR
; An example program memory address
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the
; erase command is asserted
© 2011 Microchip Technology Inc.
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