PIC24HJ32GP202-E/MM Microchip Technology, PIC24HJ32GP202-E/MM Datasheet - Page 9
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PIC24HJ32GP202-E/MM
Manufacturer Part Number
PIC24HJ32GP202-E/MM
Description
16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP202-ISO.pdf
(272 pages)
3.PIC24HJ32GP202-ISO.pdf
(8 pages)
4.PIC24HJ32GP202-ISO.pdf
(12 pages)
Specifications of PIC24HJ32GP202-E/MM
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.2
Before programming, the programmer must confirm
that the programming executive is stored in executive
memory. The procedure for this task is illustrated in
Figure
First, ICSP mode is entered. Then, the unique
Application ID Word stored in executive memory is read.
If the programming executive is resident, the correct
Application ID Word is read and programming can
resume as normal. However, if the Application ID Word is
not present, the programming executive must be
programmed to executive code memory using the
method described in
Programming Executive to
for the Application ID of each device.
Section 5.0 “Device Programming – ICSP”
the ICSP programming method.
the Application ID Word”
reading the Application ID Word in ICSP mode.
FIGURE 3-2:
© 2010 Microchip Technology Inc.
Note 1: See
3-2.
Enter ICSP™ Mode
by reading Address
Enter Enhanced
Exit ICSP Mode
Confirming the Presence of the
Programming Executive
Application ID
Application ID
Sanity Check
ICSP Mode
present?
Check the
0x8007F0
Start
End
sion”
device.
Is
Yes
TABLE 7-1: “Device IDs and Revi-
(1)
for the Application ID of each
Section 6.0 “Programming the
CONFIRMING PRESENCE
OF PROGRAMMING
EXECUTIVE
describes the procedure for
No
Prog. Executive must
Memory”. See
Section 5.11 “Reading
be Programmed
describes
Table 7-1
3.3
As illustrated in
Program/Verify mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
devices. There is no minimum time requirement for
holding at V
least P18 must elapse before presenting the key
sequence on PGDx.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more
hexadecimal format). The device will enter Program/
Verify mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19 and P7 must elapse before
presenting data on PGDx. Signals appearing on PGDx
before P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Note:
The MCLR pin is briefly driven high then low.
A 32-bit key sequence is clocked into PGDx.
MCLR is then driven high within a specified
period of time and held.
easily
Entering Enhanced ICSP Mode
When programming a device without
Peripheral Pin Select (PPS) and in
Enhanced ICSP mode, the SPI output pin
(SDOx) may toggle while the device is
being programmed.
IH
. After V
Figure
remembered
DD
IH
3-3, entering Enhanced ICSP
in case of dsPIC33F/PIC24H
is removed, an interval of at
as
0x4D434850
DS70152H-page 9
IH
must be
IH
in
,