PIC24HJ32GP302-E/SO Microchip Technology, PIC24HJ32GP302-E/SO Datasheet
PIC24HJ32GP302-E/SO
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PIC24HJ32GP302-E/SO Summary of contents
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... PIC24HJ64GPX02/X04 and © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ128GPX02/X04 High-Performance, 16-bit Microcontrollers Data Sheet DS70293E ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash program memory (up to 128 Kbytes) • Data SRAM ( Kbytes) • Boot, Secure and General Security for program Flash © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Timers/Capture/Compare/PWM: • Timer/Counters five 16-bit timers: - Can pair up to make two 32-bit timers - One timer runs as a Real-Time Clock with an external 32 ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Communication Modules: • 4-wire SPI (up to two modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes 2 • I C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing ...
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... PIC24HJ32GP302 Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except PIC24HJ32GP302/304, which include 1 Kbyte of DMA RAM. 2: Only four out of five timers are remappable. 3: Only two out of three interrupts are remappable. © 2011 Microchip Technology Inc. Remappable Peripheral ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Pin Diagrams 28-Pin SDIP, SOIC AN0/V +/CN2/RA0 REF AN1/V -/CN3/RA1 REF (1) PGED1/AN2/C2IN-/RP0 /CN4/RB0 (1) PGEC1/ AN3/C2IN+/RP1 /CN5/RB1 (1) AN4/C1IN-/RP2 /CN6/RB2 (1) AN5/C1IN+/RP3 /CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 (1) SOSCI/RP4 /CN1/PMBE/RB4 SOSCO/T1CK/CN0/PMA1/RA4 (1) PGED3/ASDA1/RP5 /CN27/PMD7/RB5 (2) 28-Pin QFN-S (1) PGED1/AN2/C2IN-/RP0 /CN4/RB0 (1) PGEC1/AN3/C2IN+/RP1 ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Pin Diagrams (Continued) (2) 44-Pin QFN (1) AN4/C1IN-/RP2 /CN6/RB2 (1) AN5/C1IN+/RP3 /CN7/RB3 (1) AN6/RP16 /CN8/RC0 (1) AN7/RP17 /CN9/RC1 (1) AN8/CV /RP18 /PMA2/CN10/RC2 REF OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin TQFP (1) AN4/C1IN-/RP2 /CN6/RB2 (1) AN5/C1IN+/RP3 /CN7/RB3 (1) AN6/RP16 /CN8/RC0 (1) AN7/RP17 /CN9/RC1 (1) AN8/CV /RP18 /PMA2/CN10/RC2 REF OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See 2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (V ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Table of Contents PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Product Families ........................................................ 5 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 15 3.0 CPU............................................................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory.............................................................................................................................................................. 53 6.0 Resets ....................................................................................................................................................................................... 59 7.0 Interrupt Controller ..................................................................................................................................................................... 67 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 105 9 ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 1-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Type Type AN0-AN12 I Analog CLKI I ST/CMOS CLKO O — OSC1 I ST/CMOS OSC2 I/O — SOSCI I ST/CMOS SOSCO O — CN0-CN30 I ST IC1-IC2 I ST IC7-IC8 I ST OCFA I ST OC1-OC4 O — INT0 ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type SCL1 I/O ST SDA1 I/O ST ASCL1 I/O ST ASDA1 I/O ST TMS I ST TCK I ST TDI I ST TDO O — C1RX I ST C1TX O — RTCC O — ANA REF C1IN- ...
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... Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family of 16-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 10 µ Tantalum R R1 MCLR C PIC24H 0.1 µF Ceramic 0.1 µF 10 Ω Ceramic 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including MCUs to supply a local power source ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with the PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first ...
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... operations to be executed in a single cycle. A block diagram of the CPU is shown in the programmer’s model for the PIC24HJ32GP302/ 304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/ X04 is shown in 3.2 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU) ...
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... The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign possible. FIGURE 3-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 3-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 3.4 CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (2) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘ ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 3.5 Arithmetic Logic Unit (ALU) The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register ...
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... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is shown in PIC24HJ64GPX02/X04 GOTO Instruction Reset Address ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.1.1 PROGRAM MEMORY ORGANIZATION The program memory space is word-addressable blocks. Although it is treated as 24 bits wide more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.2 Data Address Space The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 CPU has a separate 16 bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps are shown in ...
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... DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJ32GP302/304 DEVICES WITH 4 KB RAM Address 2 Kbyte SFR Space 4 Kbyte ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR PIC24HJ128GP202/204, PIC24HJ64GP202/204, PIC24HJ128GP502/504 AND PIC24HJ64GP502/504 DEVICES WITH 8 KB RAM MSb Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 8 Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 ...
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... TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 CN30IE CN29IE — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...
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TABLE 4-10: UART2 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U2MODE 0230 UARTEN — USIDL IREN U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — U2TXREG 0234 — — — — U2RXREG 0236 — — — ...
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... TABLE 4-13: ADC1 REGISTER MAP FOR PIC24HJ64GP202/502, PIC24HJ128GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...
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TABLE 4-15: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...
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TABLE 4-15: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...
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TABLE 4-16: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — ...
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TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...
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TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11SID 046C C1RXF11EID 046E C1RXF12SID 0470 C1RXF12EID 0472 C1RXF13SID 0474 C1RXF13EID 0476 C1RXF14SID 0478 C1RXF14EID ...
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... TABLE 4-20: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
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... TABLE 4-22: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR PIC24HPIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PMMODE 0602 BUSY IRQM<1:0> PMADDR ADDR15 CS1 0604 PMDOUT1 PMDOUT2 0606 PMDIN1 0608 PMPDIN2 060A PMAEN 060C — ...
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... C2EVT C1EVT CVRCON 0632 — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-27: PORTA REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — ...
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TABLE 4-28: PORTA REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA ...
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... Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register is not present in devices with 32K Flash (PIC24HJ32GP302/304). TABLE 4-33: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.2.6 SOFTWARE STACK In addition to its use as a working register, the W15 register in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 4.3.3 MOVE (MOV) INSTRUCTION Move instructions provide a greater degree of address- ing flexibility than other instructions ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.4 Interfacing Program and Data Memory Spaces The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 4-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H) ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to “Section 5. Flash Pro- gramming” (DS70191) “dsPIC33F/PIC24H Family Reference Manual” ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 5.2 RTSP Operation The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE bit 7 Legend Settable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY< ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY Programmers can program one row of program Flash memory at a time this necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000, W0 ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 8. “Reset” (DS70192) of the “dsPIC33F/PIC24H Family Refer- ence Manual”, which is available from the Microchip website (www ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 6-1: RCON: RESET CONTROL REGISTER bit 1 BOR: Brown-out Reset Flag bit Brown-out Reset has occurred Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit Power-on Reset has occurred Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 6.1 System Reset The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR 2 BOR SYSRST Oscillator Clock FSCM Device Status Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V crosses the BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 6-2: OSCILLATOR DELAY Symbol V POR threshold POR T POR extension time POR V BOR threshold BOR T BOR extension time BOR T Programmable power-up time delay PWRT T Fail-Safe Clock Monitor Delay FSCM Note: When the device exits condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc ...
Page 65
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 6-3: BROWN-OUT SITUATIONS V DD SYSRST V DD SYSRST V dips before PWRT expires SYSRST 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset ...
Page 66
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 6.7 Configuration Mismatch Reset To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware unexpected change in any of the registers occur (such as cell dis- turbances caused by ESD or other external events), a configuration mismatch Reset occurs. ...
Page 67
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 32. (Part III)” (DS70214) ”dsPIC33F/PIC24H Family Reference Manual” ...
Page 68
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 7-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector ...
Page 69
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 7-1: INTERRUPT VECTORS Vector IVT Address Number 0 0x000004 1 0x000006 2 0x000008 3 0x00000A 4 0x00000C 5 0x00000E 6 0x000010 7 0x000012 8 0x000014 9 0x000016 10 0x000018 11 0x00001A 12 0x00001C 13 0x00001E 14 0x000020 15 0x000022 16 0x000024 17 0x000026 18 0x000028 19 0x00002A 20 0x00002C 21 0x00002E 22 0x000030 23 0x000032 24 0x000034 25 0x000036 26 0x000038 27 0x00003A 28 0x00003C ...
Page 70
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Vector IVT Address Number 47 0x000062 48 0x000064 49 0x000066 50 0x000068 51 0x00006A 52 0x00006C 53 0x00006E 54 0x000070 55 0x000072 56 0x000074 57 0x000076 58 0x000078 59 0x00007A 60 0x00007C 61 0x00007E 62 0x000080 63 0x000082 64 0x000084 65 0x000086 66 0x000088 67 0x00008A 68 0x00008C 69 0x00008E 70 0x000090 71 0x000092 72 0x000094 73 0x000096 74 0x000098 ...
Page 71
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 7.3 Interrupt Control and Status Registers PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices implement a total of 30 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
Page 72
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
Page 73
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 R/W-0 R/W-0 — DIV0ERR DMACERR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit ...
Page 74
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...
Page 75
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 — DMA1IF AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 76
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred ...
Page 77
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit ...
Page 78
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred ...
Page 79
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 R/W-0 R/W-0 — DMA4IF PMPIF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 80
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 R/W-0 — RTCIF DMA5IF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 81
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 (1) — C1TXIF DMA7IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ ...
Page 82
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 — DMA1IE AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 83
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled ...
Page 84
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 R/W-0 R/W-0 U-0 IC8IE IC7IE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit ...
Page 85
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 ...
Page 86
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 R/W-0 R/W-0 — DMA4IE PMPIE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 87
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 R/W-0 — RTCIE DMA5IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 88
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 R/W-0 R/W-0 (1) — C1TXIE DMA7IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ ...
Page 89
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP< ...
Page 90
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP< ...
Page 91
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP< ...
Page 92
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 93
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP< ...
Page 94
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 — IC8IP<2:0> bit 15 U-0 U-1 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP< ...
Page 95
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 — T4IP<2:0> bit 15 U-0 R/W-1 R/W-0 — OC3IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP< ...
Page 96
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 — U2TXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP< ...
Page 97
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 R/W-1 R/W-0 — C1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP< ...
Page 98
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ ...
Page 99
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-25: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PMPIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 100
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-26: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — DMA5IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 101
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 — CRCIP<2:0> bit 15 U-0 R/W-1 R/W-0 — U1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP< ...
Page 102
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-28: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — DMA7IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 103
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 7-29: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...
Page 104
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level depends on the specific application and type of interrupt source ...
Page 105
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 8.0 DIRECT MEMORY ACCESS (DMA) Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 38. “Direct Memory Access (DMA) (Part III)” (DS70215) of the “ ...
Page 106
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 The DMA controller features eight identical data transfer channels. Each channel has its own set of control and status registers. Each DMA channel can be configured to copy data either from buffers stored in dual port DMA RAM to peripheral SFRs, or from peripheral SFRs to buffers in DMA RAM ...
Page 107
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 8.1 DMAC Registers Each DMAC Channel contains the following registers: • A 16-bit DMA Channel Control register (DMAxCON) • A 16-bit DMA Channel IRQ Select register (DMAxREQ) • A 16-bit DMA RAM Primary Start Address register (DMAxSTA) • A 16-bit DMA RAM Secondary Start Address register (DMAxSTB) • ...
Page 108
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 CHEN SIZE DIR bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CHEN: Channel Enable bit 1 = Channel enabled ...
Page 109
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 (1) FORCE — — bit 15 U-0 R/W-0 R/W-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FORCE: Force DMA Transfer bit ...
Page 110
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 8-3: DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 STA<15:0>: Primary DMA RAM Start Address bits (source or destination) ...
Page 111
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 8-5: DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided ...
Page 112
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 R/C-0 R/C-0 PWCOL7 PWCOL6 PWCOL5 bit 15 R/C-0 R/C-0 R/C-0 XWCOL7 XWCOL6 XWCOL5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PWCOL7: Channel 7 Peripheral Write Collision Flag bit ...
Page 113
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected ...
Page 114
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 — — — bit 15 R-0 R-0 R-0 PPST7 PPST6 PPST5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...
Page 115
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 : REGISTER 8-9: DSADR MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 bit 15 R-0 R-0 R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © ...
Page 116
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 116 © 2011 Microchip Technology Inc. ...
Page 117
... Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. FIGURE 9-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC1 POSCCLK (2) R OSC2 POSCMD< ...
Page 118
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F peripheral clock time base (F operating speed of the device, and speeds MHz are supported by the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture. Instruction execution speed or device operating frequency, F ...
Page 119
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. FIGURE 9-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2011 Microchip Technology Inc. ...
Page 120
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Fast RC Oscillator with Divide-by-N (FRCDIVN) Fast RC Oscillator with Divide-by-16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (S OSC Primary Oscillator (HS) with PLL (HSPLL) Primary Oscillator (XT) with PLL (XTPLL) ...
Page 121
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘ ...
Page 122
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 3 CF: Clock Fail Detect bit (read/clear by application FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator ...
Page 123
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 124
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV< ...
Page 125
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...
Page 126
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 9.2 Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have a safeguard lock built into the switch process ...
Page 127
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 10.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 9. “Watchdog Timer and Power Savings Modes” (DS70196) of the “ ...
Page 128
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 10.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10 ...
Page 129
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 T5MD T4MD T3MD bit 15 R/W-0 R/W-0 R/W-0 I2C1MD U2MD U1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 T5MD: Timer5 Module Disable bit ...
Page 130
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 IC8MD IC7MD — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IC8MD: Input Capture 8 Module Disable bit ...
Page 131
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 U-0 CRCMD DAC1MD — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 132
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 132 © 2011 Microchip Technology Inc. ...
Page 133
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 11.0 I/O PORTS Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 10. (DS70193) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 134
... NOP, as shown in 11.5 Input Change Notification The input change notification function of the I/O ports allows the PIC24HJ32GP302/304, PIC24HJ64GPX02/ X04 and PIC24HJ128GPX02/X04 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled ...
Page 135
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 11.6 Peripheral Pin Select Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device ...
Page 136
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Timer4 External Clock Timer5 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A ...
Page 137
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 11.6.2.2 Output Mapping In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. ...
Page 138
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 11.6.3 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24H devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • ...
Page 139
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 11.7 Peripheral Pin Select Registers The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family implement 27 registers for remappable peripheral configuration: • 14 Input Remappable Peripheral Registers: - RPINR0-RPINR1, RPINR3-RPINR4, RPINR7, RPINR10-RPINR11, RPINR18- RPINR23 and PRINR26 • 13 Output Remappable Peripheral Registers: - RPOR0-RPOR12 Note: ...
Page 140
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 141
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 142
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 143
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 144
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-6: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTERS 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 145
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 146
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 147
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-9: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 148
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-10: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 149
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-11: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 150
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 151
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 152
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 153
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTERS 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 154
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTERS 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 155
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTERS 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 156
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTERS 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 157
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTERS 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 158
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 11-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTERS 12 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 159
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 12.0 TIMER1 Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 160
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 ...
Page 161
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 13.0 TIMER2/3 AND TIMER4/5 FEATURE Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 162
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 The Timer2/3 and Timer4/5 modules can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (F In Synchronous Counter mode, the input clock is derived from the external clock input at TxCK pin ...
Page 163
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 13-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Prescaler F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers. 2: Timer Type B Timer ( and 4). 3: Timer Type C Timer ( and 5). © 2011 Microchip Technology Inc. ...
Page 164
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 13-1: TxCON: TIMER CONTROL REGISTER ( R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When T32 = 1 (in 32-bit Timer mode): ...
Page 165
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 13-2: TxCON: TIMER CONTROL REGISTER ( R/W-0 U-0 R/W-0 (2) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (2) — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (2) bit 15 TON: Timery On bit 1 = Starts 16-bit Timer ...
Page 166
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 166 © 2011 Microchip Technology Inc. ...
Page 167
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 14.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 168
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 14.1 Input Capture Registers REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER ( U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 169
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 15.0 OUTPUT COMPARE Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Output Compare” (DS70209) of the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 170
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 15.1 Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 15-1 lists the different bit settings for the Output Compare modes. Figure 15-2 illustrates the output compare operation for various modes ...
Page 171
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 15-1: OCxCON: OUTPUT COMPAREx CONTROL REGISTER ( U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 172
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 172 © 2011 Microchip Technology Inc. ...
Page 173
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to “Section 18. Serial Peripheral Interface (SPI)” (DS70206) of the “ ...
Page 174
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 175
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 16-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (3) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 176
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 16-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) ...
Page 177
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit ...
Page 178
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 178 © 2011 Microchip Technology Inc. ...
Page 179
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 17.0 INTER-INTEGRATED 2 CIRCUIT™ (I C™) Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to Section 19. “Inter-Integrated 2 Circuit™ (I C™)” (DS70195) of the “ ...
Page 180
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 2 FIGURE 17-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70293E-page 180 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision ...
Page 181
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ...
Page 182
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that is transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit ...
Page 183
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0 HS R/C-0 HS R-0 HSC IWCOL I2COV D_A bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
Page 184
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 185
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 186
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 186 © 2011 Microchip Technology Inc. ...
Page 187
... The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules avail- able in the PIC24HJ32GP302/304, PIC24HJ64GPX02/ X04 and PIC24HJ128GPX02/X04 device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as per- sonal computers, LIN 2 ...
Page 188
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 18-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 189
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 18-1: UxMODE: UART bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) ...
Page 190
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 18-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 191
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 18-2: U STA: UART x bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only) ...
Page 192
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 192 © 2011 Microchip Technology Inc. ...
Page 193
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 19.0 ENHANCED CAN (ECAN™) MODULE Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Enhanced Controller Area Network (ECAN™)” ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 19-1: ECAN™ MODULE BLOCK DIAGRAM DMA Controller TRB7 TX/RX Buffer Control Register TRB6 TX/RX Buffer Control Register TRB5 TX/RX Buffer Control Register TRB4 TX/RX Buffer Control Register TRB3 TX/RX Buffer Control Register TRB2 TX/RX Buffer Control Register ...
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... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 19.3 Modes of Operation The ECAN module can operate in one of several operation modes selected by the user. These modes include: • Initialization mode • Disable mode • Normal Operation mode • Listen Only mode • Listen All Messages mode • ...
Page 196
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 19-1: CiCTRL1: ECAN™ CONTROL REGISTER 1 U-0 U-0 R/W-0 — — CSIDL bit 15 R-1 R-0 R-0 OPMODE<2:0> bit 7 Legend Writable bit, but only ‘0’ can be written to clear the bit r = Bit is Reserved R = Readable bit W = Writable bit -n = Value at POR ‘ ...
Page 197
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Writeable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit -n = Value at POR ‘ ...
Page 198
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 19-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-1 R-0 — bit 7 Legend Writeable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit -n = Value at POR ‘ ...
Page 199
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 19-4: CiFCTRL: ECAN™ FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 DMABS<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Writeable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit -n = Value at POR ‘ ...
Page 200
... PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 19-5: CiFIFO: ECAN™ FIFO STATUS REGISTER U-0 U-0 R-0 — — bit 15 U-0 U-0 R-0 — — bit 7 Legend Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit -n = Value at POR ‘ ...