PIC24HJ64GP204-E/ML Microchip Technology, PIC24HJ64GP204-E/ML Datasheet - Page 199
![16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC24HJ64GP204-E/ML
Manufacturer Part Number
PIC24HJ64GP204-E/ML
Description
16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ64GP204-E/ML
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP204-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC24HJ64GP204-E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- Current page: 199 of 368
- Download datasheet (5Mb)
REGISTER 19-4:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-5
bit 4-0
R/W-0
U-0
—
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
DMABS<2:0>
DMABS<2:0>: DMA Buffer Size bits
111 = Reserved
110 = 32 buffers in DMA RAM
101 = 24 buffers in DMA RAM
100 = 16 buffers in DMA RAM
011 = 12 buffers in DMA RAM
010 = 8 buffers in DMA RAM
001 = 6 buffers in DMA RAM
000 = 4 buffers in DMA RAM
Unimplemented: Read as ‘0’
FSA<4:0>: FIFO Area Starts with Buffer bits
11111 = Read buffer RB31
11110 = Read buffer RB30
•
•
•
00001 = TX/RX buffer TRB1
00000 = TX/RX buffer TRB0
R/W-0
U-0
—
CiFCTRL: ECAN™ FIFO CONTROL REGISTER
C = Writeable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
‘1’ = Bit is set
R/W-0
U-0
—
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
FSA<4:0>
R/W-0
U-0
—
x = Bit is unknown
R/W-0
U-0
—
DS70293E-page 199
R/W-0
U-0
—
bit 8
bit 0
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