PIC24HJ64GP204T-I/PT Microchip Technology, PIC24HJ64GP204T-I/PT Datasheet - Page 269
![16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC24HJ64GP204T-I/PT
Manufacturer Part Number
PIC24HJ64GP204T-I/PT
Description
16-bit MCU, 64KB Flash,DMA,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
Specifications of PIC24HJ64GP204T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC24HJ64GP204T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP204T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ32GP302-ISO PDF datasheet #2
- PIC24HJ32GP302-ISO PDF datasheet #3
- PIC24HJ32GP302-ISO PDF datasheet #4
- Current page: 269 of 368
- Download datasheet (5Mb)
26.0
The PIC24H instruction set is identical to that of the
PIC24F, and is a subset of the dsPIC30F/33F
instruction set.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
Table 26-1
describing the instructions.
The PIC24H instruction set summary in
all the instructions, along with the status flags affected
by each instruction.
Most word or byte-oriented W register instructions
(including
operands:
• The first source operand which is typically a
• The second source operand which is typically a
• The destination of the result which is typically a
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could either be the file
© 2011 Microchip Technology Inc.
Note:
register ‘Wb’ without any address modifier
register ‘Ws’ with or without an address modifier
register ‘Wd’ with or without an address modifier
register ‘f’ or the W0 register, which is denoted as
‘WREG’
INSTRUCTION SET SUMMARY
This
features of the PIC24HJ32GP302/304,
PIC24HJ64GPX02/X04
PIC24HJ128GPX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see
the
(www.microchip.com)
dsPIC33F/PIC24H
Manual sections.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
barrel
shows the general symbols used in
data
shift
Microchip
sheet
instructions)
Family
summarizes
for
web
Table 26-2
families
have
the
Reference
latest
three
and
site
the
lists
of
Most bit-oriented instructions (including simple
rotate/shift instructions) have two operands:
• The W register (with or without an address
• The bit in the W register or file register
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
• The W register or file register where the literal
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand which is a register ‘Wb’
• The second source operand which is a literal
• The destination of the result (only if not the same
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
All instructions are a single word, except for certain
double word instructions, which were made double
word instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles with the additional instruction cycle(s)
executed as a NOP. Notable exceptions are the BRA
(unconditional/computed branch), indirect CALL/GOTO,
all table reads and writes and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles. Certain instructions that involve skip-
ping over the subsequent instruction require either two
or three cycles if the skip is performed, depending on
whether the instruction being skipped is a single-word or
double word instruction. Moreover, double word moves
require two cycles. The double word instructions
execute in two instruction cycles.
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
register (specified by the value of ‘k’)
value is to be loaded (specified by ‘Wb’ or ‘f’)
without any address modifier
value
as the first source operand) which is typically a
register ‘Wd’ with or without an address modifier
instructions
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
Reference
DS70293E-page 269
Manual”
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