PIC24HJ64GP502T-I/MM Microchip Technology, PIC24HJ64GP502T-I/MM Datasheet - Page 26

16 Bit MCU 40MIPS 64 KB FLASH 28 QFN-S 6x6mm T/R

PIC24HJ64GP502T-I/MM

Manufacturer Part Number
PIC24HJ64GP502T-I/MM
Description
16 Bit MCU 40MIPS 64 KB FLASH 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP502T-I/MM

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel / 12 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
4.2.6
The READC command instructs the programming
executive to read N Configuration registers or Device
ID registers, starting from the 24-bit address specified
by Addr_MSB and Addr_LS. This command can only
be used to read 8-bit or 16-bit data.
When this command is used to read Configuration
registers, the upper byte in every data word returned by
the programming executive is 0x00 and the lower byte
contains the Configuration register value.
Expected Response (4 + 3 * (N
for N odd):
0x1100
2 + N
Configuration register or Device ID Register 1
...
Configuration register or Device ID Register N
DS70152H-page 26
15
Opcode
Length
N
Addr_MSB
Addr_LS
Note:
Opcode
Field
12 11
READC COMMAND
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
N
0x1
0x3
Number of 8-bit Configuration registers
or Device ID registers to read
(maximum of 256).
MSB of 24-bit source address.
Least Significant 16 bits of 24-bit
source address.
Addr_LS
8 7
Description
Length
1)/2 words
Addr_MSB
0
4.2.7
The READP command instructs the programming
executive to read N 24-bit words of code memory,
starting from the 24-bit address specified by Addr_MSB
and Addr_LS. This command can only be used to read
24-bit data. All data returned in the response to this
command uses the packed data format described in
Section 4.2.2 “Packed Data
Expected Response (2 + 3 * N/2 words for N even):
0x1200
2 + 3 * N/2
Least significant program memory word 1
...
Least significant data word N
Expected Response (4 + 3 * (N
for N odd):
0x1200
4 + 3 * (N
Least significant program memory word 1
...
MSB of program memory word N (zero padded)
15
Opcode
Length
N
Reserved
Addr_MSB
Addr_LS
Note:
Opcode
Field
Reserved
12 11
READP COMMAND
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
1)/2
0x2
0x4
Number of 24-bit instructions to read
(maximum of 32768).
0x0
MSB of 24-bit source address.
Least Significant 16 bits of 24-bit
source address.
Addr_LS
© 2010 Microchip Technology Inc.
8 7
N
Description
Format”.
Length
1)/2 words
Addr_MSB
0

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