PIC32MX320F128LT-80I/BG Microchip Technology, PIC32MX320F128LT-80I/BG Datasheet - Page 16

• Manufacturer Part Number: PIC32MX320F128LT-80I/BG
• Description: 128 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F128LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Processor Series: PIC32MX3xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

DS61146B-page 12
Processor core:
• MIPS M4K with 5-stage pipeline
• MIPS32-compatible Release 2 Instruction Set
• MIPS16e™ Code Compression to improve code density by up to 40%
• GPR shadow registers to minimize latency for interrupt handlers
• Bit field manipulation instructions
• High-performance Multiply/Divide Unit:
• Static implementation: minimum operating frequency 0 MHz
• 2.3 to 3.6V operation with full speed over entire range
• Low-power modes including RUN, IDLE, and SLEEP
Memory:
• Unified 4GB virtual memory space
• Fixed Memory Mapping Translation (FMT) mechanism
• Flexible partitioning into kernel and user accessible memory segments for
Pre Fetch Cache:
• 16 lines, each 128-bit wide, instruction Prefetch buffer
• Ability to load and lock lines – useful to create SW breakpoints in Flash and
Interrupt Controller:
• Fully programmable interrupt controller with Single or Multi vector mode, support-
• Multiple priorities and subpriorities for each vector
• Highest priority interrupt has dedicated register set for reduced interrupt latency
DMA Controller:
• Up to 4 independent channels
• Memory-to-Memory, Memory-to-Peripheral, and Peripheral-to-Memory transfers
• Programmable trigger from any IRQ
• Chainable channels, stop on match detection, Auto-Enable mode
• Data transfers can occur while the core is in IDLE mode
• Integrated programmable CRC engine: calculates on the fly while the data is
Enhanced Parallel Master Port:
• 8- and 16-bit data interface
• Up to 16-bit address lines, expandable using GPIO lines
• 2 Chip Select lines
- Maximum issue rate of one 32x16 multiply per clock
- Maximum issue rate of one 32x32 multiply every other clock
increased application stability
minimize interrupt latency
ing up to 95 IRQs.
transferred.
© 2008 Microchip Technology Inc.