PIC32MX564F128HT-I/MR Microchip Technology, PIC32MX564F128HT-I/MR Datasheet - Page 73
![64 PINS, 128KB Flash, 32KB RAM, 80 MHz, USB, CAN, 4 DMA 64 QFN 9x9x0.9mm T/R](/photos/12/13/121325/c04-149_mr_sml.jpg)
PIC32MX564F128HT-I/MR
Manufacturer Part Number
PIC32MX564F128HT-I/MR
Description
64 PINS, 128KB Flash, 32KB RAM, 80 MHz, USB, CAN, 4 DMA 64 QFN 9x9x0.9mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX564F128HT-I/MR
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Processor Series
PIC32MX5x
Core
MIPS32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 73 of 254
- Download datasheet (6Mb)
TABLE 4-10:
Legend:
Note
3000 OC1CON
3010
3020
3200 OC2CON
3210
3220
3400 OC3CON
3410
3420
3600 OC4CON
3610
3620
3800 OC5CON
3810
3820
1:
OC1RS
OC2RS
OC3RS
OC4RS
OC5RS
OC1R
OC2R
OC3R
OC4R
OC5R
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP
31/15
ON
ON
ON
ON
ON
—
—
—
—
—
30/14
FRZ
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
SIDL
SIDL
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
—
26/10
—
—
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
—
—
24/8
OC1RS<31:0>
OC2RS<31:0>
OC3RS<31:0>
OC4RS<31:0>
OC5RS<31:0>
—
—
—
—
—
—
—
—
—
—
OC1R<31:0>
OC2R<31:0>
OC3R<31:0>
OC4R<31:0>
OC5R<31:0>
Bits
(1)
23/7
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
OC32
OC32
OC32
OC32
OC32
21/5
—
—
—
—
—
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
20/4
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
19/3
—
—
—
—
—
18/2
—
—
—
—
—
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
17/1
—
—
—
—
—
for more
16/0
—
—
—
—
—
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
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