PIC32MX664F064H-I/MR Microchip Technology, PIC32MX664F064H-I/MR Datasheet - Page 89
![64 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, Ethernet, 4 DMA 64 QFN 9x9x0.9mm TUB](/photos/12/13/121325/c04-149_mr_sml.jpg)
PIC32MX664F064H-I/MR
Manufacturer Part Number
PIC32MX664F064H-I/MR
Description
64 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, Ethernet, 4 DMA 64 QFN 9x9x0.9mm TUB
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80IMR.pdf
(254 pages)
Specifications of PIC32MX664F064H-I/MR
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN Exposed Pad
Processor Series
PIC32MX5x
Core
MIPS32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 89 of 254
- Download datasheet (6Mb)
TABLE 4-19:
Legend:
Note
35F0 DCH7SSIZ
3600 DCH7DSIZ
3610 DCH7SPTR
3620 DCH7DPTR
3630 DCH7CSIZ
3640 DCH7CPTR
3650
1:
DCH7DAT
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
DMA CHANNELS 0-7 REGISTER MAP
31/15
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
(1,2)
26/10
(CONTINUED)
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
24/8
CHSPTR<15:0>
CHDPTR<15:0>
CHCPTR<15:0>
CHSSIZ<15:0>
CHDSIZ<15:0>
CHCSIZ<15:0>
—
—
—
—
—
—
—
—
Bits
23/7
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
20/4
Section 12.1.1 “CLR, SET and INV Registers”
CHPDAT<7:0>
—
—
—
—
—
—
—
19/3
—
—
—
—
—
—
—
18/2
—
—
—
—
—
—
—
17/1
—
—
—
—
—
—
—
for more
16/0
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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