S29JL032H70TFI420 Spansion Inc., S29JL032H70TFI420 Datasheet - Page 13

• Manufacturer Part Number: S29JL032H70TFI420
• Description: IC,EEPROM,NOR FLASH,2MX16/4MX8,CMOS,TSSOP,48PIN,PLASTIC
• Manufacturer: Spansion Inc.

Specifications of S29JL032H70TFI420

• Data Bus Width: 8 bit, 16 bit
• Architecture: Boot Sector
• Interface Type: Conventional
• Access Time: 70 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 2 mA
• Mounting Style: SMD/SMT
• Memory Type: Flash
• Memory Size: 32 Mbit
• Operating Temperature: + 85 C
• Package / Case: TSOP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

May 21, 2004 S29JL032HA0
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
V
will be in the standby mode, but the standby current will be greater. The device
requires standard access time (t
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. I
mode current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of t
The system can read data t
Refer to the AC Characteristics tables for RESET# parameters and to 15 for the
timing diagram.
CC3
IH
.) If CE# and RESET# are held at V
IL
SS
in the DC Characteristics table represents the standby current specification.
±0.3 V, the device draws CMOS standby current (I
but not within V
A D V A N C E
READY
CC5
CC
(during Embedded Algorithms). The system can thus monitor RY/
± 0.3 V. (Note that this is a more restricted voltage range than
in the DC Characteristics table represents the automatic sleep
SS
±0.3 V, the standby current will be greater.
I N F O R M A T I O N
RH
after the RESET# pin returns to V
CE
) for read access when the device is in either
S29JL032H
IH
READY
, but not within V
(not during Embedded Algorithms).
CC4
CC
). If RESET# is held
± 0.3 V, the device
IH
.
RP
ACC
, the
+
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