SP706CU-L/TR Exar Corporation, SP706CU-L/TR Datasheet - Page 10

• Manufacturer Part Number: SP706CU-L/TR
• Description: Low Power Microprocessor Supervisory Circuits
• Manufacturer: Exar Corporation
• Type: Simple Reset/Power-On Resetr

Specifications of SP706CU-L/TR

• Number Of Voltages Monitored: 1
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

P
The power-fail comparator can be used for
various purposes because its output and non
inverting input are not internally connected.
The inverting input is internally connected to a
1.25V reference.
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in Figure 20. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator
drops out. Use PFO to interrupt the µP so it
can prepare for an orderly power-down.
© 2010 Exar Corporation
Fig. 19: SP705/706 Timing Diagrams with WDI tri-stated.
Fig. 18: SP705/706/813L Watchdog Timing Waveforms
OWER
-F
AIL
C
OMPARATOR
L
L
o
o
w
w
P
P
o
o
w
w
10/17
e
e
r
r
M
M
M
The manual-reset input (MR) allows RESET to
be triggered by a pushbutton switch. The
switch is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by an
external logic line. MR can be used to force a
watchdog timeout to generate a RESET pulse
in the SP705/706/813L. Simply connect WDO
to MR.
When
SP705/706/707/708 RESET output no longer
sinks current, it becomes an open circuit.
High-impedance CMOS logic inputs can drift to
undetermined voltages if left undriven. If a
pull-down resistor is added to the RESET pin,
any stray charge or leakage currents will be
shunted to ground, holding RESET LOW. The
resistor value is not critical. It should be about
100KW, large enough not to load RESET and
small enough to pull RESET to ground.
i
i
Ensuring a Valid Reset Output Down to
V
c
ANUAL
c
CC
r
r
o
o
=0V
p
p
r
r
o
o
R
V
Fig. 20: Typical Operating Circuit
c
c
CC
ESET
e
e
S
S
s
s
P
P
s
s
o
o
falls
7
7
r
r
0
0
S
S
5
5
u
u
-
-
p
p
S
S
below
e
e
P
P
r
r
v
7
v
7
i
i
0
0
s
s
o
o
8
8
r
r
-
-
y
1.1V,
y
S
S
C
C
P
P
Rev. 2.0.0
i
i
8
8
r
r
c
c
1
1
u
u
3
3
i
i
the
t
t
L
L
s
s