SST25VF040B-80-4I-SAE-T Microchip Technology, SST25VF040B-80-4I-SAE-T Datasheet - Page 16

2.7V To 3.6V 4Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R

SST25VF040B-80-4I-SAE-T

Manufacturer Part Number
SST25VF040B-80-4I-SAE-T
Description
2.7V To 3.6V 4Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R
Manufacturer
Microchip Technology

Specifications of SST25VF040B-80-4I-SAE-T

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
80MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte Block-
Erase instruction is initiated by executing an 8-bit com-
mand, 52H, followed by address bits [A
[A
©2009 Silicon Storage Technology, Inc.
MS
FIGURE 13: 32-KByte Block-Erase Sequence
FIGURE 14: 64-KByte Block-Erase Sequence
-A
15
] (A
MS
= Most Significant Address) are used to
SCK
SCK
CE#
CE#
SO
SO
SI
SI
MODE 3
MODE 0
MODE 3
MODE 0
23
-A
0
]. Address bits
MSB
MSB
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
D8
52
HIGH IMPEDANCE
HIGH IMPEDANCE
16
MSB
MSB
determine block address (BA
be V
is executed. The 64-Kbyte Block-Erase instruction is initi-
ated by executing an 8-bit command D8H, followed by
address bits [A
determine block address (BA
be V
is executed. The user may poll the Busy bit in the software
status register or wait T
self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 13 and 14 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
ADDR
ADDR
IL
IL
15 16
15 16
or V
or V
ADDR
ADDR
IH.
IH.
CE# must be driven high before the instruction
CE# must be driven high before the instruction
23 24
23 24
23
1295 63KBlkEr.0
-A
1295 32KBklEr.0
ADDR
ADDR
0
]. Address bits [A
BE
31
31
4 Mbit SPI Serial Flash
for the completion of the internal
X
X
), remaining address bits can
), remaining address bits can
SST25VF040B
MS
S71295-05-000
-A
15
] are used to
10/09

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