SST49LF008A-33-4C-EIE-T Microchip Technology, SST49LF008A-33-4C-EIE-T Datasheet - Page 18

• Manufacturer Part Number: SST49LF008A-33-4C-EIE-T
• Description: 3.0V To 3.6V 8Mbit LPC Firmware Flash 40 TSOP 10x20 Mm T/R
• Manufacturer: Microchip Technology

Specifications of SST49LF008A-33-4C-EIE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 40-TFSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase can be determined
using either Data# Polling or Toggle Bit methods. See Fig-
ure 18 for Sector-Erase timing waveforms. Any commands
written during the Sector-Erase operation will be ignored.
Block-Erase Operation
The Block-Erase Operation allows the system to erase
the device in 64 KByte uniform block size for the
SST49LF008A. The Block-Erase operation is initiated by
executing a six-byte command load sequence for Soft-
ware Data Protection with Block-Erase command (50H)
and block address. The internal Block-Erase operation
begins after the sixth WE# pulse. The End-of-Erase can
be determined using either Data# Polling or Toggle Bit
methods. See Figure 19 for timing waveforms. Any com-
mands written during the Block-Erase operation will be
ignored.
Chip-Erase
The SST49LF008A device provides a Chip-Erase opera-
tion only in PP Mode, which allows the user to erase the
entire memory array to the ‘1’s state. This is useful when
the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE#. During the internal Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 9 for the command sequence, Figure 20 for tim-
ing diagram, and Figure 28 for the flowchart. Any com-
mands written during the Chip-Erase operation will be
ignored.
©2006 Silicon Storage Technology, Inc.
18
Write Operation Status Detection
The SST49LF008A device provides two software means
to detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system Write cycle time. The
software detection includes two status bits: Data# Polling
(DQ
mode is enabled after the rising edge of WE# which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or Tog-
gle Bit read may be simultaneous with the completion of the
Write cycle. If this occurs, the system may possibly get an
erroneous result, i.e., valid data may appear to conflict with
either DQ
erroneous result occurs, the software routine should include a
loop to read the accessed location an additional two (2) times.
If both reads are valid, then the device has completed the
Write cycle, otherwise the rejection is valid.
Data# Polling (DQ
When the SST49LF008A device is in the internal Program
operation, any attempt to read DQ
plement of the true data. Once the Program operation is
completed, DQ
though DQ
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ
internal Erase operation is completed, DQ
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# pulse for Program operation. For Sector- or Chip-
Erase, the Data# Polling is valid after the rising edge of
sixth WE# pulse. See Figure 15 for Data# Polling timing
diagram and Figure 26 for a flowchart. Proper status will
not be given using Data# Polling if the address is in the
invalid range.
Toggle Bit (DQ
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# pulse
for Program operation. For Sector-, Block- or Chip-Erase,
the Toggle Bit is valid after the rising edge of sixth WE#
pulse. See Figure 16 for Toggle Bit timing diagram and Fig-
ure 26 for a flowchart.
7
) and Toggle Bit (DQ
7
or DQ
7
may have valid data immediately following the
7
6
6
. In order to prevent spurious rejection, if an
will produce true data. Note that even
)
7
)
6
8 Mbit Firmware Hub
). The End-of-Write detection
7
6
will produce a ‘0’. Once the
will produce alternating ‘0’s
7
will produce the com-
SST49LF008A
S71161-11-000
7
will produce a
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