XR16V794IV-0A-EVB Exar Corporation, XR16V794IV-0A-EVB Datasheet - Page 32

• Manufacturer Part Number: XR16V794IV-0A-EVB
• Description: Supports V794 64 Ld TQFP,ISA Interface
• Manufacturer: Exar Corporation

Specifications of XR16V794IV-0A-EVB

• Design Resources: XR17V798/794 Eval Board Schematic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM, DLD) enable.
•
•
LCR[6]: Transmit Break Enable
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains until disabled by setting LCR bit-6 to a logic 0.
•
•
4.6
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers (DLL, DLM and DLD) are selected.
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
T
Table-C
Table-D
Table-A
Table-B
T
RIGGER
ABLE
Line Control Register (LCR) - Read/Write
FCTR
B
IT
0
0
1
1
T
-7
ABLE
FCTR
B
14: T
IT
0
1
0
1
-6
RANSMIT AND
B
FCR
IT
X
0
0
1
1
0
0
1
1
0
0
1
1
-7
B
FCR
IT
X
0
1
0
1
0
1
0
1
0
1
0
1
-6
R
ECEIVE
B
FCR
IT
X
0
0
0
1
1
0
0
1
1
-5
FIFO T
32
BIT
FCR
X
0
0
1
0
1
0
1
0
1
-4
RIGGER
T
Programmable
RIGGER
via RXTRG
1 (default)
R
T
register
ABLE AND
ECEIVE
14
16
24
28
16
56
60
4
8
8
8
L
EVEL
L
Programmable
EVEL
via TXTRG
1 (default)
T
T
register
RANSMIT
RIGGER
L
EVEL
16
24
30
16
32
56
8
8
S
ELECTION
16C550, 16C2550,
16C2552, 16C554,
16C580, 16L580
16C650A, 16L651
16C654
16L2752, 16L2750,
16C2852, 16C850,
16C854, 16C864
C
OMPATIBILITY
REV. 1.0.1