XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 49

• Manufacturer Part Number: XR88C681CP/40
• Description: Dual Channel UART
• Manufacturer: Exar Corporation

Specifications of XR88C681CP/40

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8086 C Interrupt Processing
If a peripheral component requires interrupt service from
the CPU, it will assert the CPU’s INTR input (by toggling it
high).
instruction, it will assert the -INTA pin (if operating in the
“min” mode) or set the
Table 15). In either case, the -IACK input of the peripheral
will be asserted. Once this happens, the interrupting
peripheral is expected to place an “interrupt vector” byte
on D0 - D7 of the data bus. The 8086 P will read this data
and multiply this value by the number 4 in order to
Rev. 2.11
Once the CPU has completed its current
MN/-MX
INTR
CLK
-
S0, -S1, and -S2 pins to “0” (see
8086 CPU
Figure 22. Schematic of the 8086 CPU Mode (Max Mode)
AD8 - AD15
AD0 - AD7
-S0
-S1
-S2
49
CLK
-S0
-S1
-S2
DEN
DT/-R
ALE
8288 Bus Controller
determine the location of the interrupt service routine in
memory. Since this “interrupt vector” is 8 bits wide, the
8086 P can accommodate up to 256 different interrupt
vectors (0 - 255). Additionally, since each vector is
multiplied by “4”, the user is expected to reserve the first
1K
Routines/Jump Table.
Figure 23 presents a schematic of the XR88C681
DUART interfacing to a “min” Mode 8086 CPU device.
Please note that the DUART has been configured to
operate in the Z-Mode. Therefore, the user must account
for the IEI input to the DUART device.
C
D
C
D
74LS373
byte
74LS373
of
-MWTC
-MRDC
-IOWC
-IORC
-INTA
Q
Q
memory
for
XR88C681
the
-MEMR
-MEMW
-IOR
-IOW
D0 - D7
A0 - A7
D8 - D15
A8 - A15
Interrupt
Service