XRT7295ATIWTR Exar Corporation, XRT7295ATIWTR Datasheet - Page 3

• Manufacturer Part Number: XRT7295ATIWTR
• Description: DS3/SONET STS-1 Line Receiver
• Manufacturer: Exar Corporation

Specifications of XRT7295ATIWTR

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

PIN CONFIGURATION
PIN DESCRIPTION
Pin #
3,6
4,5
10
12
13
14
15
16
17
18
19
20
11
1
2
7
8
9
Rev.1.20
TMC1-TMC2
LPF1-LPF2
LOSTHR
RNDATA
RPDATA
Symbol
EXCLK
GNDD
GNDC
GNDA
REQB
RLOS
RCLK
RLOL
V
V
V
ICT
R
DD
DD
DD
IN
D
C
A
Type
O
O
O
O
O
I
I
I
I
I
I
I
Description
Analog Ground.
Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series
with 50 kW.
Test Mode Control 1 and 2. Internal test modes are enabled within the device by using
TMC1 and TMC2. Users must tie these pins to the ground plane.
PLL Filter 1 and 2. An external capacitor (0.1mF ±20%) is connected between these pins.
Receive Loss-of-signal. This pin is set high on loss of the data signal at the receive input.
(See Table 6)
Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock.
Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with
PLL clock.
Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with
EXCLK.
5V Digital Supply (±10%) for PLL Clock. Power for all circuitry running synchronously
with PLL clock.
5V Digital Supply (±10%) for EXCLK. Power for all circuitry running synchronously with
EXCLK.
External Reference Clock. A valid DS3 (44.736MHz ±100ppm) or STS-1 (51.84MHz +
100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to V
/2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns.
Receive Clock. Recovered clock signal to the terminal equipment.
Receive Negative Data. Negative pulse data output to the terminal equipment. (See
Figure 11.)
Receive Positive Data. Positive pulse data output to the terminal equipment. (See
Figure 11)
In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK,
RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-cir-
cuit testing. There is an internal pull-up on this pin.
Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low
places the equalizer in the data path.
Loss-of-signal Threshold Control. The voltage forced on this pin controls the input loss-
of-signal threshold. Three settings are provided by forcing GND, V
must be set to the desired level upon power-up and should not be changed during opera-
tion.
5V Analog Supply (±10%).
GNDD
GNDC
GNDA
TMC1
TMC2
RLOS
RLOL
LPF1
LPF2
20 Lead SOJ (Jedec, 0.300”)
R
IN
10
1
2
3
4
5
6
7
8
9
3
20
19
18
17
16
15
14
13
12
11
V
LOSTHR
REQB
ICT
RPDATA
RNDATA
RCLK
EXCLK
V
V
DD
DD
DD
A
C
D
XRT7295AT
DD
/2, or V
DD
. This pin
DD