DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 78
DP83934CVUL20
Manufacturer Part Number
DP83934CVUL20
Description
Manufacturer
National Semiconductor
Datasheet
1.DP83934CVUL20.pdf
(104 pages)
Specifications of DP83934CVUL20
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Lead Free Status / RoHS Status
Not Compliant
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9 0 AC and DC Specifications
MEMORY WRITE BMODE
Note 1 For successive read operations MWR remains high
Note 2 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing)
Number
T9
T11
T11b
T12
T12b
T15
T32
T33
T36
T37
BSCK to Address Valid Hold Time
BSCK to ADS Low
BSCK to ECS Low
BSCK to ADS High
BSCK to ECS High
ADS High Width
RDYi Setup to BSCK
RDYi Hold from BSCK
BSCK to Memory Write Data Valid Hold Time
(Note 2)
BSCK to MWR (Write) Valid (Note 1)
e
0 SYNCHRONOUS MODE (one wait-state shown)
Parameter
(Continued)
78
Min
45
19
2
5
3
20 MHz
Max
26
26
19
24
29
50
24
Min
35
17
3
3
3
25 MHz
Max
24
24
17
22
27
48
22
TL F 11719– 60
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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