PC16550DV63 National Semiconductor, PC16550DV63 Datasheet
PC16550DV63
Specifications of PC16550DV63
Related parts for PC16550DV63
PC16550DV63 Summary of contents
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... M CMOS process Can also be reset to 16450 Mode under software control Note This part is patented Basic Configuration TRI-STATE is a registered trademark of National Semiconductor Corp C 1995 National Semiconductor Corporation TL C 8652 Features Capable of running all existing 16450 software Y Pin for pin compatible with the existing 16450 except ...
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ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS 4 0 TIMING WAVEFORMS 5 0 BLOCK DIAGRAM 6 0 PIN DESCRIPTIONS 7 0 CONNECTION DIAGRAMS 8 0 REGISTERS 8 1 Line Control Register 8 ...
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Absolute Maximum Ratings Temperature Under Bias Storage Temperature All Input or Output Voltages with Respect Power Dissipation Electrical Characteristics ...
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AC Electrical Characteristics Symbol Parameter t Address Strobe Width ADS t Address Hold Time Delay from Address AR t Address Setup Time Delay from Address AW t Chip Select Hold ...
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AC Electrical Characteristics Symbol Parameter Transmitter t Delay from WR WR (WR THR Reset Interrupt t Delay from RD RD (RD IIR) to Reset IR Interrupt (THRE) t Delay from Initial INTR Reset to Transmit IRS ...
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Timing Waveforms (Continued) Applicable Only When ADS is Tied Low Applicable Only When ADS is Tied Low Write Cycle Read Cycle 8652 – 8652 – 6 ...
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Timing Waveforms (Continued) Note 1 See Write Cycle Timing Note 2 See Read Cycle Timing Receiver Timing Transmitter Timing MODEM Control Timing 8652 – 8652 – 8652 – 9 ...
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Timing Waveforms (Continued) RCVR FIFO First Byte (This Sets RDR) RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set) Receiver Ready (Pin 29) FCR0 Note 1 This is the reading of the last byte in ...
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Timing Waveforms (Continued) Receiver Ready (Pin 29) FCR0 Note 1 This is the reading of the last byte in the FIFO Note 2 If FCR0 RCLKs e e SINT Transmitter Ready (Pin 24) FCR0 Transmitter ...
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Block Diagram Note Applicable pinout numbers are included within parenthesis 8652 – 16 ...
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Pin Descriptions The following describes the function of all UART pins Some of these descriptions reference internal circuits In the following descriptions a low represents a logic 0 (0V nominal) and a high represents a logic 1 ( ...
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Pin Descriptions (Continued) OUT 2 Output 2 Pin 31 This user-designated output that can be set to an active low by programming bit 3 (OUT 2) of the MODEM Control Register to a high level A Master Re- ...
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Connection Diagrams TQFP Package Order Number PC16550DVEF See NS Package Number VEF44A Register Signal Interrupt Enable Register Interrupt Identification Register FIFO Control Line Control Register MODEM Control Register Line Status Register MODEM Status Register SOUT INTR (RCVR Errs) ...
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14 ...
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Registers The system programmer may access any of the UART reg- isters summarized in Table II via the CPU These registers control UART operations including transmission and recep- tion of data Each register bit in Table II has ...
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Registers (Continued) Bit 7 This bit is the Divisor Latch Access Bit (DLAB) It must be set high (logic 1) to access the Divisor Latches of the Baud Generator during a Read or Write operation It must be ...
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Registers (Continued) FIFO Interrupt Mode Identification Only Register Priority Bit 3 Bit 2 Bit 1 Bit 0 Interrupt Type Level None Highest Receiver Line Status Second ...
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Registers (Continued) When the CPU accesses the IIR the UART freezes all inter- rupts and indicates the highest priority pending interrupt to the CPU While this CPU access is occurring the UART records new interrupts but does not ...
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Registers (Continued) Bit 7 This bit is the complement of the Data Carrier Detect (DCD) input If bit 4 of the MCR is set this bit is equivalent to OUT 2 in the MCR 8 ...
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Typical Applications (Continued) 20 ...
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Physical Dimensions inches (millimeters) Plastic Dual-In-Line Package (N) Order Number PC16550DN NS Package Number N40A 44-Lead Plastic Chip Carrier (V) Order Number PC16550DV NS Package Number V44A 21 ...
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