SAA7118EEB-T NXP Semiconductors, SAA7118EEB-T Datasheet - Page 137

• Manufacturer Part Number: SAA7118EEB-T
• Description: Video ICs COMPONENT VID DECODER W/COMB F
• Manufacturer: NXP Semiconductors
• Type: Multi-Standard Video Decoderr

Specifications of SAA7118EEB-T

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-700
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Not Compliant
• Other names: SAA7118E/V1,518

NXP Semiconductors
Table 119. Vertical input window start; register set A [98h[7:0]; 99h[3:0]] and B [C8h[7:0]; C9h[3:0]]
[1]
Table 120. Vertical input window length; register set A [9Ah[7:0]; 9Bh[3:0]] and B [CAh[7:0]; CBh[3:0]]
[1]
Table 121. Horizontal output window length; register set A [9Ch[7:0]; 9Dh[3:0]] and B [CCh[7:0]; CDh[3:0]]
[1]
[2]
SAA7118_7
Product data sheet
Vertical input acquisition window
definition offset in Y (vertical)
direction
Line offset = 0
Line offset = 1
Maximum line offset = 4095
Vertical input acquisition window
definition input window length in
Y (vertical) direction
No input lines
1 input line
Maximum possible number of input
lines = 4095
Horizontal output acquisition
window definition number of
desired output pixels in
X (horizontal) direction
No output
Odd lengths are allowed, but will be
filled up to even lengths
Maximum possible number of input
pixels = 4095
For trigger condition: STRC[1:0] 90h[1:0] = 00; YO + YS > (number of input lines per field
conditions: YO > (number of input lines per field
For trigger condition: STRC[1:0] 90h[1:0] = 00; YO + YS > (number of input lines per field
conditions: YS > (number of input lines per field
Reference for counting are luminance samples.
If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated.
[1]
[2]
10.7.8 Subaddresses 9Ch to 9Fh
[1]
[1]
Control bits
A [99h[3:0]] and
B [C9h[3:0]]
YO11 YO10 YO9
0
0
1
Control bits
A [9Bh[3:0]] and
B [CBh[3:0]]
YS11 YS10 YS9
0
0
1
Control bits
A [9Dh[3:0]] and
B [CDh[3:0]]
XD11 XD10 XD9
0
0
1
0
0
1
0
0
1
0
0
1
2), will result in field dropping.
2), will result in field dropping.
Rev. 07 — 7 July 2008
0
0
1
0
0
1
0
0
1
Multistandard video decoder with adaptive comb filter
YO8
0
0
1
YS8
0
0
1
XD8
0
0
1
A [98h[7:0]] and B [C8h[7:0]]
YO7
0
0
1
A [9Ah[7:0]] and B [CAh[7:0]]
YS7
0
0
1
A [9Ch[7:0]] and B [CCh[7:0]]
XD7
0
0
1
YO6
0
0
1
YS6
0
0
1
XD6
0
0
1
YO5
YS5
XD5
0
0
1
0
0
1
0
0
1
2), will result in field dropping. Other trigger
2), will result in field dropping. Other trigger
YO4
0
0
1
YS4
0
0
1
XD4
0
0
1
YO3
0
0
1
YS3
0
0
1
XD3
0
0
1
SAA7118
© NXP B.V. 2008. All rights reserved.
YO2
0
0
1
YS2
0
0
XD2
0
1
0
1
YO1
0
0
1
YS1
0
0
1
XD1
0
0
1
137 of 177
YO0
0
1
1
YS0
0
1
1
XD0
0
1
1