ADV7179BCPZ-REEL Analog Devices Inc, ADV7179BCPZ-REEL Datasheet - Page 44

• Manufacturer Part Number: ADV7179BCPZ-REEL
• Manufacturer: Analog Devices Inc

Specifications of ADV7179BCPZ-REEL

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 40
• Lead Free Status / RoHS Status: Compliant

ADV7174/ADV7179
APPENDIX 5—TELETEXT
TELETEXT INSERTION
t
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears t
the horizontal signal. Time TTX
the source that is gated by the TTXREQ signal in order to
deliver TTX data.
With the programmability offered with the TTXREQ signal on
the rising/falling edges, the TTX data is always inserted at the
correct position of 10.2 μs after the leading edge of horizontal
sync pulse, thus enabling a source interface with variable pipe-
line delays.
The width of the TTXREQ signal must always be maintained to
allow the insertion of 360 (to comply with the Teletext standard
PAL-WST) Teletext bits at a text data rate of 6.9375 Mbits/s.
This is achieved by setting TC03–TC00 to 0. The insertion
window is not open if the Teletext enable bit (MR35) is set to 0.
PD
is the time needed by the ADV7174/ADV7179 to interpolate
TTX
TTXREQ
CVBS/Y
HSYNC
DATA
SYNTTXOUT
t
t
TTX
SYNTTXOUT
PD
TELETEXT VBI LINE
= PIPELINE DELAY THROUGH ADV7174/ADV7179
DEL
t
PD
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
= 10.2 μs after the leading edge of
= 10.2 μ s
DEL
TTX
is the pipeline delay time by
ST
10.2 μ s
t
SYNTTXOUT
TTX
DEL
t
Figure 60. Teletext Functionality
PD
Figure 59. Teletext VBI Line
Rev. B | Page 44 of 52
RUN-IN CLOCK
45 BYTES (360 BITS) – PAL
PROGRAMMABLE PULSE EDGES
ADDRESS AND DATA
TELETEXT PROTOCOL
The relationship between the TTX bit clock (6.9375 MHz) and
the system clock (27 MHz) for 50 Hz is
Thus, 37 TTX bits correspond to 144 clocks (27 MHz) and each
bit has a width of almost four clock cycles. The ADV7174/
ADV7179 uses an internal sequencer and variable phase inter-
polation filter to minimize the phase jitter and thus generate a
band-limited signal that can be output on the CVBS and Y
outputs.
At the TTX input, the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that TTX
Bits 10, 19, 28, and 37 are carried by three clock cycles and all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are 47, 56, 65, and 74. This scheme holds
for all following cycles of 37 TTX bits until all 360 TTX bits are
completed. All Teletext lines are implemented in the same way.
Individual control of Teletext lines is controlled by Teletext
setup registers.
⎛
⎜
⎝
(
. 6
27
9375
MHz
×
4
10
⎞
⎟
⎠
6
=
. 6
. 6
75
75
MHz
×
10
6
)
=
. 1
027777