AD73460BB-80 Analog Devices Inc, AD73460BB-80 Datasheet - Page 12

• Manufacturer Part Number: AD73460BB-80
• Manufacturer: Analog Devices Inc

Specifications of AD73460BB-80

• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Digital
• Sample Rate: 64KSPS
• Input Voltage Range: 0.822V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 16b
• Supply Current: 54mA
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 119
• Package Type: BGA
• Number Of Channels: 6
• Lead Free Status / RoHS Status: Not Compliant

AD73460
Analog Sigma-Delta Modulator
The AD73460 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73460, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to f
(Figure 3a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 3b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in-band sufficiently to ensure good
dynamic performance from the part (Figure 3c).
Figure 4 shows the various stages of filtering that are employed
in a typical AD73460 application. In Figure 4a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial over-
sampling rate and the bandwidth of interest. In Figure 4b, the
signal and noise-shaping responses of the sigma-delta modulator
are shown. The signal response provides further rejection of any
high frequency signals while the noise-shaping will push the inher-
ent quantization noise to an out-of-band position. The detail of
Figure 4c shows the response of the digital decimation filter
INTEREST
INTEREST
INTEREST
BAND
BAND
BAND
OF
OF
OF
Figure 3. Sigma-Delta Noise Reduction
NOISE-SHAPING
DIGITAL FILTER
a.
b.
c.
S
/2 = DMCLK/16
DMCLK/16
DMCLK/16
DMCLK/16
f
f
S
f
S
S
/2
/2
/2
–12–
(sinc-cubed response) with nulls every multiple of DMCLK/256,
which is the decimation filter update rate. The final detail in
Figure 4d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord-
ing to the user’s requirements and available MIPS. The filtering
in Figures 4a through 4c is implemented in the AD73460.
Decimation Filter
The digital filter used in the AD73460 carries out two important
functions. Firstly, it removes the out-of-band quantization noise,
which is shaped by the analog modulator, and secondly, it deci-
mates the high frequency bit stream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits. Its Z
transform is given as: [(1–Z
mal group delay of 25 µs.
b. Analog Sigma-Delta Modulator Transfer Function
f
B
f
a. Analog Antialias Filter Transfer Function
B
f
= 4kHz
B
d. Final Filter LPF (HPF) Transfer Function
= 4kHz
= 4kHz
c. Digital Decimator Transfer Function
f
B
Figure 4. DC Frequency Responses
= 4kHz
f
SIGNAL TRANSFER FUNCTION
SINTER
f
SFINAL
= DMCLK/256
= 8kHz
–32
NOISE TRANSFER FUNCTION
)/(1–Z
f
SINTER
–1
)]
3
= DMCLK/256
. This ensures a mini-
f
SINIT
f
SINIT
= DMCLK/8
= DMCLK/8
REV. A