LM4546AVHX/NOPB National Semiconductor, LM4546AVHX/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM4546AVHX/NOPB
• Manufacturer: National Semiconductor

Specifications of LM4546AVHX/NOPB

• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.2V
• Single Supply Voltage (max): 5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

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SDATA_IN Slot 1: Status Address / Slot Request Bits
This slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read
request in the previous SDATA_OUT frame, slot 1. Bits 11
and 10 are slot request bits that support Sample Rate Con-
version (SRC) functionality. If bit 11 is set to 0, then the
controller should respond with a valid PCM left sample in slot
3 of the next frame. If bit 10 is set to 0, then the controller
should respond with a valid PCM right sample in slot 4 of the
next frame. If bits 11 or 10 are set to 1, the controller should
not send data in the next frame. Bits 9 through 2 are unused.
Bits 1 and 0 are reserved and should be set to 0.
SDATA_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SDATA_OUT
frame, slot 1.
18:12
Bits
Bit
9:2
1,0
15
14
13
12
11
19
11
10
FIGURE 7. Start of Audio Input Frame
Slot 1 data valid
Slot 2 data valid
Slot 3 data valid Left Audio PCM Data is valid
Slot 4 data valid
Control Register
Slot 3 Request
Slot 4 Request
bit (PCM right)
Codec Ready
bit (PCM left)
Description
Description
Request bits
Other Slot
Reserved
Reserved
Index
Bit
Echo of Control Register for
frame, 1 = Controller should
frame, 1 = Controller should
valid slot 3 data in the next
valid slot 4 data in the next
0 = Controller should send
0 = Controller should send
not send slot 3 data in the
not send slot 4 data in the
Right Audio PCM Data is
0=Not Ready, 1=Ready
Status Address is valid
Status Data is valid
which data is being
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next frame
next frame
Comment
Comment
returned.
Unused
valid
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SDATA_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal to be
digitized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the left ADC. This is a
20-bit slot, where the digitized 18-bit PCM data is output from
the codec MSB first and the last remaining 2 bits will zeros.
SDATA_IN Slot 4: PCM Record Right Channel
This slot contains the right ADC sample data. The signal dig-
itized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the right ADC. This is
a 20-bit slot, where the digitized 18-bit PCM data is output
from the codec MSB first and the last remaining 2 bits will
zeros.
SDATA_IN Slots 5-12: Reserved
These SDATA_IN slots are set to "0" as they are reserved for
future use.
AC Link Low Power Mode
Register Descriptions
Reset Register (00h)
Writing any value to this register causes a register reset which
changes all of the registers back to their default values. If this
register is read, the LM4546 will return a value of 0D50h in-
dicating that National 3D Sound is implemented and 18bit
data is supported by both the ADCs and DACs.
Master Volume Registers (02h, 06h)
These two registers allow the output levels from LINE_OUT,
and MONO_OUT to be attenuated or muted. There are 6-bits
of volume control, plus one mute bit. It is a 5-bit volume range,
where each step is nominally 1.5dB and each output can be
Bits
19:4
Bits
19:2
Bits
19:2
3:0
1:0
1:0
FIGURE 8. AC Link Powerdown Timing
Control Register
Right Channel
PCM Record
Left Channel
PCM Record
Description
Description
Description
Read Data
Reserved
Reserved
Reserved
data
data
18 bit audio sample from left
18 bit audio sample from
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Comment
Comment
Comment
right ADC
ADC
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