AD1985JSTZREEL Analog Devices Inc, AD1985JSTZREEL Datasheet - Page 8

• Manufacturer Part Number: AD1985JSTZREEL
• Manufacturer: Analog Devices Inc

Specifications of AD1985JSTZREEL

• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.97/4.5V
• Single Supply Voltage (max): 3.63/5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Compliant

AD1985
TIMING PARAMETERS
Guaranteed over operating temperature range.
Table 14.
Parameter
RESET ACTIVE LOW PULSE WIDTH
RESET INACTIVE TO SDATA_IN OR BIT_CLK ACTIVE DELAY
SYNC ACTIVE HIGH PULSE WIDTH
SYNC LOW PULSE WIDTH
SYNC INACTIVE TO BIT_CLK STARTUP DELAY
BIT_CLK FREQUENCY
BIT_CLK PERIOD
BIT_CLK OUTPUT JITTER
BIT_CLK HIGH PULSE WIDTH
BIT_CLK LOW PULSE WIDTH
SYNC FREQUENCY
SYNC PERIOD
SETUP TO FALLING EDGE OF BIT_CLK
HOLD FROM FALLING EDGE OF BIT_CLK
BIT_CLK RISE TIME
BIT_CLK FALL TIME
SYNC RISE TIME
SYNC FALL TIME
SDATA_IN RISE TIME
SDATA_IN FALL TIME
SDATA_OUT RISE TIME
SDATA_OUT FALL TIME
END OF SLOT 2 TO BIT_CLK, SDATA_IN LOW
SETUP TO TRAILING EDGE OF RESET (APPLIES TO SYNC, SDATA_OUT)
RISING EDGE OF RESET TO HIGH-Z DELAY
PROPAGATION DELAY
RESET RISE TIME
OUTPUT VALID DELAY FROM RISING EDGE OF BIT_CLK TO SDI VALID
RESET INACTIVE TO BIT_CLK STARTUP DELAY
1
2
Guaranteed, not tested.
Output jitter directly dependent on crystal input jitter; maximum specified for noncrystal operation.
1, 2
Rev. A | Page 8 of 48
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RST_LOW
RST2CLK
SYNC_HIGH
SYNC_LOW
SYNC2CLK
CLK_PERIOD
CLK_HIGH
CLK_LOW
SYNC_PERIOD
SETUP
HOLD
RISECLK
FALLCLK
RISESYNC
FALLSYNC
RISEDIN
FALLDIN
RISEDOUT
FALLDOUT
S2_PDOWN
SETUP2RST
OFF
CO
TRI2ACTV
Min
162.8
162.8
33
33
10
5
2
2
2
2
2
2
2
2
0
15.0
Typ
1.0
1.3
19.5
12.288
81.4
750
42
38
48.0
20.8
2.5
4
4
4
4
4
4
4
4
Max
2000
48
48
6
6
6
6
6
6
6
6
1.0
25.0
15
50
15
25
ns
ns
ns
ps
ns
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
µs
µs
µs
MHz
µs
µs