AD73422BB-40 Analog Devices Inc, AD73422BB-40 Datasheet - Page 10

• Manufacturer Part Number: AD73422BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

AD73422
samples at DMCLK/8. Its bitstream output is filtered and deci-
mated by a Sinc-cubed decimator to provide a sample rate se-
lectable from 64 kHz, 32 kHz, 16 kHz or 8 kHz (based on an
AMCLK of 16.384 MHz).
The DAC channel features a Sinc-cubed interpolator which
increases the sample rate from the selected rate to the digital
sigma-delta modulator rate of DMCLK/8. The digital sigma-
delta modulator’s output bitstream is fed to a single-bit DAC
whose output is reconstructed/filtered by two stages of low-pass
filtering (switched capacitor and continuous time) before being
applied to the differential output driver.
VOUTN1
REFOUT
REFCAP
VOUTP1
VFBN1
VFBP1
VINN1
VINP1
INVERTING
Figure 3. Analog Front End Configuration
REFCAP
REFOUT
VOUTP1
VOUTN1
VOUTP2
VOUTN2
OP AMPS
V
VFBN1
VFBP1
VFBN2
VFBP2
REF
VINN1
VINP1
VINN2
VINP2
V
V
REF
REF
LOOP-BACK
ANALOG
SELECT
+6/–15dB
REFERENCE
PGA
+6/–15dB
+6/–15dB
Figure 2. Functional Block Diagram of Analog Front End Section
PGA
PGA
ANALOG
ANALOG
GAIN
LOOP-
LOOP-
BACK
BACK
REFERENCE
1
CONTINUOUS
LOW-PASS
INVERT
FILTER
TIME
CONTINUOUS
CONTINUOUS
LOW-PASS
LOW-PASS
FILTER
FILTER
GAIN
GAIN
TIME
TIME
AFE SECTION
1
1
AD73422
SINGLE-ENDED
SINGLE-ENDED
SINGLE-ENDED
ENABLE
V
REF
ENABLE
ENABLE
GAIN TAP
INVERT
INVERT
ANALOG
CAPACITOR
CAPACITOR
LOW-PASS
LOW-PASS
SWITCHED
SWITCHED
0/38dB
FILTER
FILTER
PGA
AFE SECTION
AD73422
–10–
0/38dB
0/38dB
PGA
PGA
1-BIT
1-BIT
DAC
DAC
Each channel also features two programmable gain elements,
Analog Gain Tap (AGT) and Digital Gain Tap (DGT), which,
when enabled, add a signed and scaled amount of the input
signal to the DAC’s output signal. This is of particular use in
line impedance balancing when interfacing the AFE to Sub-
scriber Line Interface Circuits (SLICs).
FUNCTIONAL DESCRIPTION - AFE
Encoder Channels
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input anti-
alias requirements are reduced such that a simple single-pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a switched
capacitor PGA which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table I, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
MODULATOR
MODULATOR
SIGMA-DELTA
SIGMA-DELTA
MODULATOR
MODULATOR
DIGITAL
DIGITAL
SIGMA-
SIGMA-
DELTA
DELTA
ANALOG
ANALOG
GAIN
GAIN
1
1
DECIMATOR
DECIMATOR
POLATOR
POLATOR
INTER-
INTER-
SERIAL
PORT
I/O
SDI
SDIFS
SCLK2
ARESET
AMCLK
SE
SDO
SDOFS
REV. 0