AD73411BB-40 Analog Devices Inc, AD73411BB-40 Datasheet - Page 31

• Manufacturer Part Number: AD73411BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73411BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay be-
• EZ-ICE emulation introduces an 8 ns propagation delay
• EZ-ICE emulation ignores RESET and BR when single-
• EZ-ICE emulation ignores RESET and BR when in Emula-
• EZ-ICE emulation ignores the state of target BR in certain
ANALOG FRONT END (AFE) INTERFACING
The AFE section of the AD73411 features a voiceband input/
output channel, each with 16-bit linear resolution. Connectivity
to the AFE section from the DSP is uncommitted, thus allowing
the user the flexibility of connecting in the mode or configuration
of their choice. This section will detail several configurations—
with no extra AFE channels configured and with two extra AFE
channels configured (using an external AD73322 dual AFE).
DSP SPORT to AFE Interfacing
The SCLK, SDO, SDOFS, SDI and SDIFS pins of SPORT2
must be connected to the Serial Clock, Receive Data, Receive
Data Frame Sync, Transmit Data, and Transmit Data Frame
Sync pins respectively of either SPORT0 or SPORT1. The SE
pin may be controlled from a parallel output pin or flag pin such
as FL0–2 or, where SPORT2 power-down is not required, it
can be permanently strapped high using a suitable pull-up
resistor. The ARESET pin may be connected to the system
hardware reset structure or it may also be controlled using a
dedicated control line. In the event of tying it to the global system
reset, it is advisable to operate the device in mixed mode, which
allows a software reset, otherwise there is no convenient way of
resetting the AFE section.
Cascade Operation
Where it is required to configure extra analog I/O channels to
the existing two channels on the AD73411, it is possible to
cascade up to seven more channels (using single channel AD73311
or dual channel AD73322 AFEs) by using the scheme described
in Figure 24. It is necessary, however, to ensure that the timing
tween your target circuitry and the DSP on the RESET signal.
between your target circuitry and the DSP on the BR signal.
stepping.
tor Space (DSP halted).
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
SECTION
DSP
DT
RFS
FL1
TFS
SCLK
DR
FL0
ARESET
SDOFS
SDIFS
SCLK
SDO
SDI
SE
SECTION
AFE
of the SE and ARESET signals is synchronized at each device in
the cascade. A simple D-type flip-flop is sufficient to sync each
signal to the master clock AMCLK, as in Figure 23.
Connection of a cascade of devices to a DSP, as shown in Figure
24, is no more complicated than connecting a single device.
Instead of connecting the SDO and SDOFS to the DSP’s Rx
port, these are now daisy-chained to the SDI and SDIFS of the
next device in the cascade. The SDO and SDOFS of the final
device in the cascade are connected to the DSP section’s Rx port
to complete the cascade. SE and ARESET on all devices are fed
from the signals that were synchronized with the AMCLK using
the circuit as described above. The SCLK from only one device
need be connected to the DSP section’s SCLK input(s) as all
devices will be running at the same SCLK frequency and phase.
Interfacing to the AFE’s Analog Inputs and Outputs
The AFE section of the AD73411 offers a flexible interface for
microphone pickups, line level signals, or PSTN line interfaces.
This section will detail some of the configurations that can be
used with the input and output sections.
The AD73411 features both differential inputs and outputs to
provide optimal performance and avoid common-mode noise. It is
also possible to interface either inputs or outputs in single-ended
mode. This section details the choice of input and output configu-
rations and also gives some tips toward successful configuration of
the analog interface sections.
FL0
SECTION
D1
D2
DSP
TO ARESET
CONTROL
CONTROL
FL1
74HC74
AMCLK
AMCLK
TO SE
DSP
DSP
TFS
DR
RFS
DT
SCLK
Q1
Q2
ARESET
CLK
CLK
D
D
74HC74
74HC74
1/2
1/2
SDOFS
SDOFS
SDIFS
SDIFS
SCLK
SCLK
SDO
SDO
SDI
SDI
Q
Q
ADDITIONAL
SECTION
AD73322
DEVICE 1
DEVICE 2
CODEC
AFE
SE SIGNAL
SYNCHRONIZED
TO AMCLK
ARESET SIGNAL
SYNCHRONIZED
TO AMCLK
AD73411
AMCLK
SE
ARESET
AMCLK
SE
ARESET
AD73411