XC3S500E-4CPG132C Xilinx Inc, XC3S500E-4CPG132C Datasheet - Page 135
![FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA](/photos/6/70/67095/pk373-cp132_sml.jpg)
XC3S500E-4CPG132C
Manufacturer Part Number
XC3S500E-4CPG132C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4CPG132C
Package
132CSBGA
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
92
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
92
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
132-TFBGA, CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1484
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4CPG132C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4CPG132C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 95: Test Methods for Timing Measurement at I/Os (Continued)
The capacitive load (C
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C
are used for all measurements. Any delay that the test fix-
ture might contribute to test measurements is subtracted
from those measurements to produce the final timing num-
bers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V
with the parameters used in
not confuse V
model with V
table. A fourth parameter, C
parameters describe all relevant output test conditions. IBIS
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
DIFF_SSTL18_I
DIFF_SSTL2_I
L
value of zero. High-impedance probes (less than 1 pF)
Descriptions of the relevant symbols are as follows:
V
V
V
V
V
R
V
The load capacitance (C
According to the PCI specification.
Signal Standard
REF
ICM
M
L
H
T
T
(IOSTANDARD)
– Low-level test voltage at Input pin
– Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
– Termination voltage
– High-level test voltage at Input pin
– Voltage of measurement point on signal transition
– The common mode input voltage
– The reference voltage for setting the input switching threshold
R
REF
REF
REF
, R
(the input-switching threshold) from the
(the termination voltage) from the IBIS
REF
L
) is connected between the output
, and V
L
) at the Output pin is 0 pF for all signal standards.
Table 95
REF
V
REF
, is always zero. The four
MEAS
-
-
(V)
) correspond directly
(V
T
, R
V
V
T
REF
REF
, and V
V
Inputs
L
(V)
– 0.5
– 0.5
M
www.xilinx.com
). Do
V
V
REF
REF
V
models are found in the Xilinx development software as well
as at the following link:
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
2. Record the time to V
3. Simulate the same signal standard with the output
4. Record the time to V
5. Compare the results of steps 2 and 4. Add (or subtract)
H
(V)
+ 0.5
+ 0.5
http://www.xilinx.com/support/download/index.htm
driver connected to the test setup shown in
Use parameter values V
C
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including V
and V
load.
the increase (or decrease) in delay to (or from) the
REF
is zero.
MEAS
R
values) or capacitive value to represent the
T
50
50
(Ω)
Outputs
DC and Switching Characteristics
M
MEAS
.
T
, R
.
V
T
1.25
, and V
T
0.9
(V)
REF
M
from
, R
Inputs and
REF
Outputs
Table
Figure
V
V
V
M
, C
ICM
ICM
(V)
REF
95.
73.
,
135