LM2742MTC National Semiconductor, LM2742MTC Datasheet - Page 10

• Manufacturer Part Number: LM2742MTC
• Manufacturer: National Semiconductor

Specifications of LM2742MTC

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Application Information
THEORY OF OPERATION
The LM2742 is a voltage-mode, high-speed synchronous
buck regulator with a PWM control scheme. It is designed for
use in set-top boxes, thin clients, DSL/Cable modems, and
other applications that require high efficiency buck convert-
ers. It has power good (PWRGD), and output shutdown
(SD). Current limit is achieved by sensing the voltage V
across the low side FET. During current limit the high side
gate is turned off and the low side gate turned on. The soft
start capacitor is discharged by a 95µA source (reducing the
maximum duty cycle) until the current is under control.
START UP
When V
logic high the soft start capacitor begins charging through an
internal fixed 10µA source. During this time the output of the
error amplifier is allowed to rise with the voltage of the soft
start capacitor. This capacitor, C
and can be determined approximately by:
An application for a microprocessor might need a delay of
3ms, in which case C
a 100ms delay might be more appropriate, in which case
C
flag is forced low and is released when the voltage reaches a
set value. At this point this chip enters normal operation mode
and the Power Good flag is released.
Since the output is floating when the LM2742 is turned off, it
is possible that the output capacitor may be precharged to
some positive value. During start-up, the LM2742 operates
fully synchronous and will discharge the output capacitor to
some extent depending on the output voltage, soft start ca-
pacitance, and the size of the output capacitor.
NORMAL OPERATION
While in normal operation mode, the LM2742 regulates the
output voltage by controlling the duty cycle of the high side
and low side FETs. The equation governing output voltage is:
The PWM frequency is adjustable between 50kHz and 2MHz
and is set by an external resistor, R
pin and ground. The resistance needed for a desired frequen-
cy is approximately:
MOSFET GATE DRIVERS
The LM2742 has two gate drivers designed for driving N-
channel MOSFETs in a synchronous mode. Power for the
drivers is supplied through the BOOT pin. For the high side
gate (HG) to fully turn on the top FET, the BOOT voltage must
be at least one V
voltage can be supplied by a separate, higher voltage source,
or supplied from a local charge pump structure. In a system
such as a desktop computer, both 5V and 12V are usually
available. Hence if Vin was 5V, the 12V supply could be used
for BOOT. 12V is more than 2*Vin, so the HG would operate
SS
would be 400nF. (390 10%) During soft start the PWRGD
CC
exceeds 4.2V and the shutdown pin SD sees a
V
O
GS(th)
= 0.6 x (R
SS
greater than Vin. (BOOT
would be 12nF. For a different device,
FB1
SS
+ R
, determines soft start time,
FB2
FADJ
) / R
, between the FREQ
FB1
≥
2*Vin) This
DS
10
correctly. For a BOOT of 12V, the initial gate charging current
is 2A, and the initial gate discharging current is typically 6A.
In a system without a separate, higher voltage, a charge pump
(bootstrap) can be built using a diode and small capacitor,
Figure 1. The capacitor serves to maintain enough voltage
between the top FET gate and source to control the device
even when the top FET is on and its source has risen up to
the input voltage level.
The LM2742 gate drives use a BiCMOS design. Unlike some
other bipolar control ICs, the gate drivers have rail-to-rail
swing, ensuring no spurious turn-on due to capacitive cou-
pling.
POWER GOOD SIGNAL
The power good signal is the or-gated flag representing over-
voltage and under-voltage protection. If the output voltage is
18% over it's nominal value, V
that value, V
return to a logic high whenever the feedback pin voltage is
between 70% and 118% of 0.6V. The power good pin is an
open drain output that can be pulled up to logic voltages of
5V or less with a 10kΩ resistor.
UVLO
The 4.2V turn-on threshold on V
0.6V. Therefore, if V
LO mode. UVLO consists of turning off the top FET, turning
off the bottom FET, and remaining in that condition until V
rises above 4.2V. As with shutdown, the soft start capacitor
is discharged through a FET, ensuring that the next start-up
will be smooth.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the low
side FET while it is on. The R
hence the current through the FET can be determined as:
The current through the low side FET while it is on is also the
falling portion of the triangle wave inductor current. The cur-
rent limit threshold is determined by an external resistor,
R
constant current of 50 µA is forced through R
fixed voltage drop. This fixed voltage is compared against
V
DS
CS
, connected between the switch node and the I
and if the latter is higher, the current limit of the chip has
FIGURE 1. BOOT Supplied by Charge Pump
FB
= 0.41V, the power good flag goes low. It will
CC
V
drops below 3.6V, the chip enters UV-
DS
= I * R
DSON
FB
CC
of the FET is a known value,
DSON
= 0.7V, or falls 30% below
has a built in hysteresis of
CS
20087502
, causing a
SEN
pin. A
CC