LM1238AAD/NA National Semiconductor, LM1238AAD/NA Datasheet - Page 7

• Manufacturer Part Number: LM1238AAD/NA
• Manufacturer: National Semiconductor

Specifications of LM1238AAD/NA

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Package Type: MDIP
• Lead Free Status / RoHS Status: Not Compliant

Typical Performance
Characteristics
otherwise specified (Continued)
Figure 2 and Figure 3 show the case where the Horizontal
and Vertical inputs are logic levels. Figure 2 shows the
smaller pin 24 voltage superimposed on the horizontal
blanking pulse input to the neck board with R
C
17
= 0.1µF. Note where the voltage at pin 24 is clamped to
FIGURE 8. ABL Gain Reduction Curve
FIGURE 7. Red Cathode Response
V
CC
= 5V, T
A
= 25˚C unless
H
= 4.7K and
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about 1 volt when the pin is sinking current. Figure 3 shows
the smaller pin 1 voltage superimposed on the vertical blank-
ing input to the neck board with C
Figure 4 and Figure 5 show the case where the horizontal
and vertical inputs are from deflection. Figure 4 shows the
pin 24 voltage which is derived from a horizontal flyback
pulse of 35 volts peak to peak with R
jumpered. Figure 5 shows the pin 1 voltage which is derived
from a vertical flyback pulse of 55 volts peak to peak with C
Figure 6 shows the pin 23 clamp input voltage superimposed
on the neck board clamp logic input pulse. R
should be chosen to limit the pin 23 voltage to about 2.5V
peak to peak. This corresponds to the application circuit
given in Figure 9.
CATHODE RESPONSE
Figure 7 shows the response at the red cathode for the
application circuit in Figures 9, 10. The input video risetime is
1.5 nanoseconds. The resulting leading edge has a 10.1
nanosecond risetime and a 8% overshoot, while the trailing
edge has a 8.3 nanosecond risetime and a 2% overshoot
with an LM2469 driver.
ABL GAIN REDUCTION
The ABL function reduces the contrast level of the LM1238
as the voltage on pin 22 is lowered from V
volts. Figure 8 shows the amount of gain reduction as the
voltage is lowered from V
is small until V
slope increases. Many system designs will require about 3 to
5 dB of gain reduction in full beam limiting. Additional attenu-
ation is possible, and can be used in special circumstances.
However, in this case, video performance such as video
linearity and tracking between channels will tend to depart
from normal specifications.
OSD PHASE LOCKED LOOP
Table 2 shows the recommended horizontal scan rate
ranges (in kHz) for each combination of PLL register setting,
0x081E [1:0], and the pixels per line register setting, 0x0802
[7:6]. While the OSD PLL may lock for other combinations,
the performance of the loop will be improved if these recom-
mendations are followed. NR means the combination of PLL
and PPL is not recommended for any scan rate.
= 1500pF and R
PLL Range
TABLE 2. OSD Register Recommendations
1
2
3
22
V
reaches the knee anound 3.7V, where the
89-100
30-45
45-89
= 120K.
130
CC
(5.0V) to 2V. The gain reduction
82-100
30-41
41-82
Pixels per Line
176
4
jumpered and R
79-100
30-40
40-79
H
240
= 8.2K and C
CC
31
to around 2
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= 1K and
82-100
V
30-41
41-82
352
= 4.7K.
17
4