AD9912BCPZ Analog Devices Inc, AD9912BCPZ Datasheet - Page 17

• Manufacturer Part Number: AD9912BCPZ
• Manufacturer: Analog Devices Inc

Specifications of AD9912BCPZ

• Lead Free Status / RoHS Status: Compliant

The input to the DDS is a 48-bit FTW that provides the accu-
mulator with a seed value. On each cycle of f
adds the value of the FTW to the running total of its output.
For example, given an FTW = 5, the accumulator increments
the count by 5 sec on each f
reaches the upper end of its capacity (2
rolls over, retaining the excess. The average rate at which the
accumulator rolls over establishes the frequency of the output
sinusoid. The following equation defines the average rollover
rate of the accumulator and establishes the output frequency
(f
Solving this equation for FTW yields
For example, given that f
FTW = 5,471,873,547,255 (0x04FA05143BF7).
The relative phase of the sinusoid can be controlled numerically,
as well. This is accomplished using the phase offset function of
the DDS (a programmable 14-bit value (Δphase); see the I/O
Register Map section). The resulting phase offset, ΔΦ (radians),
is given by
DIGITAL-TO-ANALOG (DAC) OUTPUT
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. This series is
translated to an analog signal by means of a digital-to-analog
converter (DAC).
The DAC outputs its signal to two pins driven by a balanced
current source architecture (see the DAC output diagram in
Figure 41). The peak output current derives from a combination
of two factors. The first is a reference current (I
established at the DAC_RSET pin, and the second is a scale
factor that is programmed into the I/O register map.
The value of I
between the DAC_RSET pin and ground. The DAC_RSET pin
DDS
) of the DDS:
FTW
∆
f
DDS
Φ
=
=
2
=
π



round
 ∆


DAC_REF
FTW
2
48
phase
2
14







is set by connecting a resistor (R
2
f
48
S







TUNING WORD
S
FREQUENCY
= 1 GHz and f
f
S
DDS
f
(FTW)
S
cycle. Over time, the accumulator








48
48
48-BIT ACCUMULATOR
DDS
in this case) and then
= 19.44 MHz, then
S
, the accumulator
DAC_REF
48
48
) that is
D
DAC_REF
Q
Figure 40. DDS Block Diagram
)
19
Rev. D | Page 17 of 40
OFFSET
PHASE
14
19
CONVERSION
AMPLITUDE
ANGLE TO
is internally connected to a virtual voltage reference of 1.2 V
nominal, so the reference current can be calculated by
Note that the recommended value of I
leads to a recommended value for R
The scale factor consists of a 10-bit binary number (FSC)
programmed into the DAC full-scale current register in the
I/O register map. The full-scale DAC output current (I
is given by
Using the recommended value of R
output current can be set with 10-bit granularity over a range of
approximately 8.6 mA to 31.7 mA. 20 mA is the default value.
RECONSTRUCTION FILTER
The origin of the output clock signal produced by the AD9912
is the combined DDS and DAC. The DAC output signal appears
as a sinusoid sampled at f
determined by the frequency tuning word (FTW) that appears
at the input to the DDS. The DAC output is typically passed
through an external reconstruction filter that serves to remove
the artifacts of the sampling process and other spurs outside the
filter bandwidth. If desired, the signal can then be brought back
on-chip to be converted to a square wave that is routed internally
to the output clock driver or the 2× DLL multiplier.
DAC_OUT
I
I
I
FS
DAC
DAC
/2 + I
14
_
_
CODE
REF
FS
50
CURRENT
REGISTERS
AND LOGIC
SWITCH
DAC I-SET
ARRAY
=
(14-BIT)
=
DAC
I
DAC
R
INTERNAL
DAC
1
_
I
f
FS
50Ω
S
2 .
REF
Figure 41. DAC Output
_
/2
REF



S
. The frequency of the sinusoid is
72
CONTROL
SWITCH
AVDD3
DAC_RSET
DAC_OUT
DAC_OUTB
CODE
AVSS
+
49
52
192
I
FS
1024
INTERNAL
DAC_REF
FSC
DAC_REF
50Ω
I
FS
DAC_REF
/2



CURRENT
SWITCH
, the full-scale DAC
ARRAY
of 10 kΩ.
is 120 μA, which
I
FS
51
/2 – I
DAC_OUTB
AD9912
CODE
DAC_FS
)