AT52BR3244T-85-CI Atmel, AT52BR3244T-85-CI Datasheet
AT52BR3244T-85-CI
Specifications of AT52BR3244T-85-CI
Related parts for AT52BR3244T-85-CI
AT52BR3244T-85-CI Summary of contents
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... Flash + 4-megabit (256K x 16)/ 8-megabit (512K x 16) SRAM Stack Memory AT52BR3244 AT52BR3244T AT52BR3248 AT52BR3248T Not Recommended for New Designs. New Designs Should Use AT52BR3224(T)/3228(T) Rev. 2471E–STKD–10/02 1 ...
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AT52BR3244(T)/ AT52BR3248(T) (Top View) Pin Configurations l AT52BR3244(T)/3248( A20 A11 A15 B A16 A8 A10 C WE RDY/BSY D SGND RESET E NC VPP A19 F SLB SUB SOE G A18 A17 ...
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Description The AT52BR3244(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM in a stacked 66-ball CBGA package. The AT52BR3248(T) combines a 32-megabit Flash (2M x 16) and a 8-megabit SRAM in a stacked 66-ball CBGA package. The ...
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Flash The 32-megabit Flash memory is organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data Description appears on I/O0 - I/O7. The ...
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Flash Memory Block Diagram OUTPUT BUFFER INPUT A0 - A20 BUFFER ADDRESS LATCH Y-DECODER X-DECODER 2471E–STKD–10/02 AT52BR3244(T)/3248(T) I/O0 - I/O15/A-1 INPUT BUFFER IDENTIFIER REGISTER STATUS REGISTER COMMAND REGISTER DATA COMPARATOR WRITE STATE MACHINE Y-GATING PLANE B SECTORS PLANE A ...
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Device Operation READ: The 32-megabit Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs ...
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VPP PIN: The circuitry of the 32-megabit Flash is designed so that the device can be programmed or erased from the V is less than or equal to ...
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... PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see “Operating Modes” on page 16 (for hardware operation) or “Software Product Identification Entry/Exit” ...
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Noise filter: pulses of less than 15 ns (typical) on the inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs ...
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Command Definition in Hex 1st Bus Cycle Command Bus Sequence Cycles Addr Read 1 Addr Chip Erase 6 555 Sector Erase 6 555 Word Program 4 555 Enter Single Pulse 6 555 Program Mode Single Pulse Word 1 Addr Program ...
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Protection Register Addressing Table Word Use Block 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Note: 1. All address lines not specified in the above table must be 0 when accessing the ...
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Bottom Boot 32-megabit Flash (24M + 8M ) Sector Address Table Plane ...
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Bottom Boot 32-megabit Flash (24M + 8M ) Sector Address Table (Continued) Plane ...
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Top Boot 32-megabit Flash (24M + 8M) Sector Address Table Plane Sector B SA0 B SA1 B SA2 B SA3 B SA4 B SA5 B SA6 B SA7 B SA8 B SA9 B SA10 B SA11 B SA12 B SA13 ...
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Top Boot 32-megabit Flash (24M + 8M) Sector Address Table (Continued) Plane Sector B SA37 B SA38 B SA39 B SA40 B SA41 B SA42 B SA43 B SA44 B SA45 B SA46 B SA47 A SA48 A SA49 A ...
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... X can Refer to AC programming waveforms on page 23 12.0V ± 0.5V Manufacturer Code: 001FH, Device Code: 00D8H - AT4952BR3244/3248; 00D9H - AT52BR3244T/3248T. 5. See details under “Software Product Identification Entry/Exit” on page 24. can be left unconnected or 0V ≤ 12V ± 0.5V. AT52BR3244(T)/3248(T) 16 AT52BR3244(T)-85, 90 Ind. ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CMOS SB1 Standby Current TTL SB2 Standby Current TTL SB3 CC ( Active Read ...
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AC Read Characteristics Symbol Parameter t Address to Output Delay ACC ( Output Delay CE ( Output Delay OE (3)( Output Float DF Output Hold from OE ...
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Input Test Waveforms and Measurement Level t Output Test Load Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: 1. This parameter is characterized and is not 100% tested. 2471E–STKD–10/02 ...
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AC Word Load Characteristics Symbol Parameter Address, OE Setup Time AS OES t Address Hold Time AH t Chip Select Setup Time CS t Chip Select Hold Time CH t Write Pulse Width (WE or CE) WP ...
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Program Cycle Characteristics Symbol Parameter t Word Programming Time (0V < Word Programming Time (V BPVPP t Address Setup Time AS t Address Hold Time AH t Data Setup Time DS t Data Hold Time DH t ...
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Sector or Chip Erase Cycle Waveforms ( A20 555 WORD 0 Notes must be high only when WE and ...
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Data Polling Characteristics Symbol Parameter t Data Hold Time Hold Time OEH ( Output Delay OE t Write Recovery Time WR Notes: 1. These parameters are characterized and not 100% tested. 2. See t ...
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... The device does not remain in identification mode if pow- ered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 001FH(x16) Device Code: 00D8H- AT52BR3244/3248; 00D9H-AT52BR3244T/3248T. 6. Either one of the Product ID Exit commands can be used. AT52BR3244(T)/3248(T) 24 Sector Lockdown Enable Algorithm LOAD DATA F0 TO ...
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Status Bit Table Read Address In Plane A While Programming in Plane A I/O7 Programming in Plane B DATA Erasing in Plane A Erasing in Plane B DATA Erase Suspended & Read Erasing Sector Erase Suspended & Read DATA Non-erasing ...
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SRAM The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K words by 16 bits. The SRAM uses high-performance full CMOS process technol- Description ogy and is designed for high-speed and low-power circuit technology ...
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Absolute Maximum Ratings Symbol Parameter Input/Output Voltage IN OUT V Power Supply CC T Operating Temperature A T Storage Temperature STG P Power Dissipation D Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may ...
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DC Electrical Characteristics T = -40°C to 85°C A Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current CC I Average Operating Current CC1 I Standby Current (TTL Input Standby ...
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AC Characteristics T = -40°C to 85°C, Unless Otherwise Specified A # Symbol Parameter 1 t Read Cycle Time Address Access Time Chip Select Access Time ACS 4 t Output Enable to Output Valid ...
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AC Test Loads Note: AT52BR3244(T)/3248( OUT (1) CL Including jig and scope capacitance 1.8V TM 4091 Ohm 3273 Ohm 2471E–STKD–10/02 ...
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Timing Diagrams (1),(4) Read Cycle 1 ADDRESS SCS1 SCS2 SUB, SLB SOE HIGH-Z DATA OUT (1) (2) ( Read Cycle 2 ADDRESS DATA OUT PREVIOUS DATA (1) (2) ( Read Cycle 3 SCS1 SUB, SLB SCS2 ...
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Write Cycle 1 (SWE Controlled) ADDRESS SCS1 SCS2 SUB, SLB SWE DATA IN DATA OUT Write Cycle 2 (SCS1, SCS2 Controlled) ADDRESS SCS1 SCS2 SUB, SLB SWE DATA IN DATA OUT Notes write occurs during the overlap of ...
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Data Retention Electric Characteristic T = -40°C to 85°C A Symbol Parameter V V for Data Retention Data Retention Current CCDR tCDR See Data Retention Timing Diagram tR Operating Recovery Time Note: 1. Typical values are under ...
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SRAM The 8-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 512K words by 16 bits. The SRAM uses high-performance full CMOS process technol- Description ogy and is designed for high-speed and low-power circuit technology ...
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Absolute Maximum Ratings Symbol Parameter Input/Output Voltage IN OUT V Power Supply CC T Operating Temperature A T Storage Temperature STG P Power Dissipation D Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may ...
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DC Electrical Characteristics T = -40°C to 85°C A Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Operating Power Supply Current CC I Average Operating Current CC1 I Standby Current (TTL Input Standby ...
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AC Characteristics T = -40°C to 85°C, Unless Otherwise Specified A # Symbol Parameter 4 t Output Enable to Output Valid SLB, SUB Access Time Chip Select to Output in Low Z CLZ 7 ...
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AC Test Loads Note: AT52BR3244(T)/3248( OUT (1) CL Including jig and scope capacitance 2.8V TM 1045 Ohm 2048 Ohm 2471E–STKD–10/02 ...
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Timing Diagrams (1),(4) Read Cycle 1 ADDRESS SCS1 SCS2 SUB, SLB SOE HIGH-Z DATA OUT (1) (2) ( Read Cycle 2 ADDRESS DATA OUT PREVIOUS DATA (1) (2) ( Read Cycle 3 SCS1 SUB, SLB SCS2 ...
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Write Cycle 1 (SWE Controlled) ADDRESS SCS1 SCS2 SUB, SLB SWE DATA IN DATA OUT Write Cycle 2 (SCS1, SCS2 Controlled) ADDRESS SCS1 SCS2 SUB, SLB SWE DATA IN DATA OUT Notes write occurs during the overlap of ...
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Data Retention Electric Characteristic T = -40°C to 85°C A Symbol Parameter V V for Data Retention Data Retention Current CCDR tCDR See Data Retention Timing Diagram tR Operating Recovery Time Note: 1. Typical values are under ...
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... Ordering Information t ACC (ns) Ordering Code 85 AT52BR3244-85CI 90 AT52BR3244-90CI 110 AT52BR3244-11CI 85 AT52BR3244T-85CI 90 AT52BR3244T-90CI 110 AT52BR3244T-11CI 85 AT52BR3248-85CI 90 AT52BR3248-90CI 85 AT52BR3248T-85CI 90 AT52BR3248T-90CI 66C4 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA) AT52BR3244(T)/3248(T) 42 Flash Boot Flash Plane Block Architecture SRAM Bottom 24M + 8M 256K x 16 Bottom 24M + 8M ...
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Packaging Information 66C4 – CBGA Marked A1 Identifier E Top View 1.10 REF Bottom View TITLE 2325 Orchard Parkway San Jose, CA 95131 R 2471E–STKD–10/02 ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...