AT25010AN-10SU-2.7 SL383 Atmel, AT25010AN-10SU-2.7 SL383 Datasheet - Page 6

• Manufacturer Part Number: AT25010AN-10SU-2.7 SL383
• Manufacturer: Atmel

Specifications of AT25010AN-10SU-2.7 SL383

• Density: 1Kb
• Interface Type: Serial (SPI)
• Organization: 128x8
• Access Time (max): 40ns
• Frequency (max): 10MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Supply Current: 10mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Compliant

5. Functional Description
6
AT25010A/020A/040A/080A
The AT25010A/020A/040A is designed to interface directly with the synchronous serial periph-
eral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25010A/020A/040A utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in
with the MSB first and start with a high-to-low CS transition.
Table 5-1.
Note:
WRITE ENABLE (WREN): The device will power up in the write disable state when V
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
The WP pin must be held high during a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the block write protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruction.
Table 5-2.
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Bit 7
X
“A” represents MSB address bit A8.
Instruction Set for the AT25010A/020A/040A
Status Register Format
Bit 6
X
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 A011
0000 A010
Bit 5
X
Table
Bit 4
X
5-1. All instructions, addresses, and data are transferred
Operation
Reset Write Enable Latch
Read Status Register
Set Write Enable Latch
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bit 3
BP1
Bit 2
BP0
WEN
Bit 1
Bit 0
RDY
5087E–SEEPR–7/09
CC
is