M27V101-200B1 STMicroelectronics, M27V101-200B1 Datasheet - Page 5

M27V101-200B1

Manufacturer Part Number
M27V101-200B1
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of M27V101-200B1

Density
1Mb
Organization
128Kx8
Interface Type
Parallel
Bus Type
Parallel
In System Programmable
External
Access Time (max)
200ns
Package Type
PDIP
Reprogramming Technique
OTP
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
50mA
Pin Count
32
Mounting
Through Hole
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Table 7. Read Mode DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; V
Note: 1. V
Table 8A. Read Mode AC Characteristics
(T
Note: 1. V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
t
t
Symbol
Symbol
A
EHQZ
GHQZ
V
t
t
t
t
will not occur.
I
I
V
AVQV
GLQV
AXQX
V
ELQV
I
I
CC1
CC2
I
V
IH
= 0 to 70 °C or –40 to 85°; V
I
CC
LO
PP
OH
LI
OL
2. Maximum DC voltage on Output is V
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
IL
(2)
(2)
(2)
CC
CC
must be applied simultaneously with or before V
must be applied simultaneously with or before V
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
t
ACC
t
t
t
Alt
t
t
OH
CE
OE
DF
DF
Address Valid to Output Valid
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output
Transition
Parameter
Parameter
CC
CC
CC
= 3.3V ± 10%; V
= 3.3V ± 10%; V
+0.5V.
(1)
(1)
E = V
E > V
PP
PP
f = 5MHz, V
and removed simultaneously or after V
and removed simultaneously or after V
IL
0V
CC
Test Condition
0V
, G = V
Test Condition
E = V
E = V
PP
I
I
OH
OH
I
PP
OL
V
– 0.2V, V
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
= V
E = V
PP
V
G = V
G = V
E = V
E = V
= –400µA
= –100µA
= 2.1mA
= V
V
OUT
IL
IL
IN
= V
IL
, G = V
, G = V
CC
, I
CC
CC
IH
IL
IL
IL
IL
CC
OUT
)
V
CC
)
V
CC
CC
3.6V
IL
IL
= 0mA,
3.6V
Min
0
0
0
- 90
V
(3)
Max
CC
90
90
45
30
30
M27V101
–0.3
Min
PP
PP
2.4
– 0.7V
2
.
.
Min
0
0
0
-100
V
CC
Max
±10
±10
Max
0.8
0.4
100
100
15
20
10
50
30
30
1
+ 1
M27V101
Unit
ns
ns
ns
ns
ns
ns
Unit
mA
mA
µA
µA
µA
µA
V
V
V
V
V
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