AT45DB321D-SU SL383 Atmel, AT45DB321D-SU SL383 Datasheet - Page 4

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AT45DB321D-SU SL383

Manufacturer Part Number
AT45DB321D-SU SL383
Description
Manufacturer
Atmel
Datasheet

Specifications of AT45DB321D-SU SL383

Density
32Mb
Access Time (max)
6ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC EIAJ
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
4M
Supply Current
15mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Compliant
3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1.
4
SECTOR ARCHITECTURE
RDY/BUSY
AT45DB321D
SECTOR 62 = 128 Pages
SECTOR 63 = 128 Pages
SECTOR 1 = 128 Pages
SECTOR 2 = 128 Pages
SECTOR 0b = 120 Pages
SECTOR 0a = 8 Pages
65,536/67,584 bytes
65,536/67,584 bytes
65,536/67,584
65,536/67,586 bytes
61,440/63,360 bytes
4,096/4,224 bytes
RESET
Memory Architecture Diagram
GND
VCC
SCK
WP
CS
bytes
PAGE (512/528 BYTES)
BUFFER 1 (512/528 BYTES)
SECTOR 0a
SI
BLOCK ARCHITECTURE
Block = 4,096/4,224 bytes
FLASH MEMORY ARRAY
BLOCK 1,022
BLOCK 1,023
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
I/O INTERFACE
8 Pages
BUFFER 2 (512/528 BYTES)
SO
PAGE ARCHITECTURE
Page = 512/528 bytes
PAGE 8,190
PAGE 8,191
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
3597M–DFLASH–3/09

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