M25PE80-VMN6P NUMONYX, M25PE80-VMN6P Datasheet - Page 6

• Manufacturer Part Number: M25PE80-VMN6P
• Description: Flash Mem Serial-SPI 3.3V 8M-Bit 1M x 8 8ns 8-Pin SOIC N Tray
• Manufacturer: NUMONYX

Specifications of M25PE80-VMN6P

• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 4096
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Compliant

Description
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Description
The M25PE80 is an 8-Mbit (1 Mb ×8) serial paged flash memory accessed by a high speed
SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the page write or
page program instruction. The page write instruction consists of an integrated page erase
cycle followed by a page program cycle.
The memory is organized as 16 sectors that are further divided up into 16 subsectors each
(256 subsectors in total). Each sector contains 256 pages and each subsector contains 16
pages. Each page is 256-byte wide. Thus, the whole memory can be viewed as consisting
of 4096 pages, or 1 048 576 bytes.
The memory can be erased a page at a time, using the page erase instruction, a subsector
at a time, using the subsector erase instruction, a sector at a time, using the sector erase
instruction, or as a whole, using the bulk erase instruction.
The memory can be write protected by either hardware or software using a mix of volatile
and non-volatile protection features, depending on the application needs. The protection
granularity is of 64 Kbytes (sector granularity).
Important note
This datasheet details the functionality of the M25PE80 devices, based on the previous T7Y
process or based on the current T9HX process (available since June 2007). Delivery of
parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
What are the changes?
The M25PE80 in T9HX process offers the following additional features:
Suppressed feature:
For more details please refer to PCNMPG062148.
the whole memory array is partitioned into 4-Kbyte subsectors
two new instructions: write status register (WRSR) and 4-Kbyte subsector erase (SSE)
Status register: 4 bits can be written (BP0, BP1, BP2, SRWD)
WP input (pin 3): write protection limits are extended, depending on the value of the
BP0, BP1, BP2, SRWD bits. The WP write protection remains the same if bits (BP2,
BP1, BP0) are set to (0, 0, 1)
smaller die size allowing assembly into an SO8N package.
The write protection (defined by the WL and LD lock bits) of the 4-Kbyte subsectors in
the top and bottom sectors is no longer offered.
M25PE80