NAND512W3A2DZA6F NUMONYX, NAND512W3A2DZA6F Datasheet - Page 26

• Manufacturer Part Number: NAND512W3A2DZA6F
• Manufacturer: NUMONYX

Specifications of NAND512W3A2DZA6F

• Cell Type: NAND
• Density: 512Mb
• Access Time (max): 12us
• Interface Type: Parallel
• Address Bus: 26b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 64M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / RoHS Status: Compliant

Device operations
6.5
Figure 14. Block erase operation
6.6
26/53
RB
I/O
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
Once the erase operation has completed the status register can be checked for errors.
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for t
of t
issued, refer to
Block Erase
Setup Code
BLBH4
One bus cycle is required to setup the Block Erase command
Only three bus cycles are required to input the block address. The first cycle (A0 to A7)
is not required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the
last address cycle I/O2 to I/O7 must be set to V
One bus cycle is required to issue the confirm command to start the P/E/R controller.
60h
depends on the operation that the device was performing when the command was
Table 21
Block Address
Inputs
for the values.
Confirm
Code
D0h
BLBH4
after the Reset command is issued. The value
(Erase Busy time)
Figure
IL
tBLBH3
Busy
.
NAND512xxA2D, NAND01GxxA2C
14):
Read Status Register
70h
SR0
ai07593