SLUFM1GU2UA STEC, SLUFM1GU2UA Datasheet - Page 10

• Manufacturer Part Number: SLUFM1GU2UA
• Manufacturer: STEC

Specifications of SLUFM1GU2UA

• Lead Free Status / RoHS Status: Compliant

SLUFMxGU2U(I)-y
USB Flash Module
Datasheet
3.2.2 Wear Leveling
The SLC NAND flash devices that are being used in the USB Flash Module are guaranteed for 100,000
Write/Erase cycles per block. This means that after approximately 100,000 erase cycles, the erase block
has a higher probability for errors than the error rate that is typical to the flash. While 100,000 write/erase
cycles may be good for consumer data storage, such as digital cameras, MP3 players, etc., it is not
sufficient for industrial and embedded applications where data is constantly written to the device and long
product life is required.
For example, operating systems that use a file system, will update the File Allocation Table (FAT) every
time a write is done to the device. Without any wear leveling in place, the area on the flash where the FAT
table is located would wear out faster than other areas, reducing the lifetime of the entire flash device.
To overcome this limitation, the flash management algorithm needs to make sure that each block in the
device ages, i.e. is ―worn out‖, at the same rate. The built-in wear leveling scheme makes sure that with
every write to the flash, the youngest block is used. This ensures that the full flash media is used
uniformly, so that one area of the flash will not reach the endurance limits prematurely before other areas.
3.2.3 Error Correction
The USB 2.0 controller implements an advanced Error Correction scheme, based on the BCH error
correct algorithm. The ECC engine can correct up to 12 bits per 512 bytes (symbol based). To ensure the
fastest performance, correction is done on-the-fly, in hardware only.
Each time the host application writes a sector of 512 bytes to the USB Flash Module, a unique ECC
signature is created by the ECC engine and written together with the data to the flash. When the data is
read back by the host, the ECC engine creates again the unique ECC signature. It will then compare the
original written signature with the newly created signature, and sets an error flag if the two signatures are
not the same. Correction of the data is done on-the-fly when the error flag is set, and the data presented
to the host will be the same as the original written data. This powerful Error Correction scheme results in
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an overall error rate of less than 1 in 10
bits, read.
61000-05386-113, December 2009
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