STK11C68-5KF45M Cypress Semiconductor Corp, STK11C68-5KF45M Datasheet - Page 8

• Manufacturer Part Number: STK11C68-5KF45M
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK11C68-5KF45M

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: CDIP
• Operating Temperature Classification: Military
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -55C to 125C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 85mA
• Lead Free Status / RoHS Status: Compliant

STK11C68-M
The STK11C68-M has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as an ordinary static
RAM. In nonvolatile operation, data is transferred from
SRAM to EEPROM or from EEPROM to SRAM. In this
mode SRAM functions are disabled.
SRAM READ
The STK11C68-M performs a READ cycle whenever
E and G are LOW while W is HIGH. The address
specified on pins A
data bytes will be accessed. When the READ is
initiated by an address transition, the outputs will be
valid after a delay of t
READ is initiated by E or G, the outputs will be valid at
t
The data outputs will repeatedly respond to address
changes within the t
for transitions on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
The STK11C68-M is a high speed memory and there-
fore must have a high frequency bypass capacitor of
approximately 0.1 F connected between DUT V
and V
possible. As with all high speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM WRITE
A write cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W go HIGH at the end of the cycle. The
data on pins DQ
is valid t
or t
It is recommended that G be kept HIGH during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
NONVOLATILE STORE
The STK11C68-M STORE cycle is initiated by execut-
ing sequential READ cycles from six specific address
locations.
STK11C68-M implements nonvolatile operation while
remaining pin-for-pin compatible with standard 8Kx8
SRAMs. During the STORE cycle, an erase of the
ELQV
DVEH
or at t
SS
DVWH
using leads and traces that are as short as
before the end of an E controlled WRITE.
GLQV
By relying on READ cycles only, the
before the end of a W controlled WRITE
, whichever is later (READ CYCLE #2).
0-7
0-12
AVQV
will be written into the memory if it
AVQV
determines which of the 8192
access time without the need
WLQZ
(READ CYCLE #1). If the
after W goes LOW.
DEVICE OPERATION
CC
4-38
previous nonvolatile data is first performed, followed
by a program of the nonvolatile elements. The pro-
gram operation copies the SRAM data into nonvolatile
elements. Once a STORE cycle is initiated, further
input and output are disabled until the cycle is com-
pleted.
Because a sequence of reads from specific addresses
is used for STORE initiation, it is important that no
other read or write accesses intervene in the sequence
or the sequence will be aborted and no STORE or
RECALL will take place.
To initiate the STORE cycle the following READ se-
quence must be performed:
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although
it is not necessary that G be LOW for the sequence to
be valid. After the t
the SRAM will again be activated for READ and WRITE
operation.
HARDWARE PROTECT
The STK11C68-M offers hardware protection against
inadvertent STORE cycles through V
STORE cycle will not be initiated, and one in progress
will discontinue, if V
typical, characterized value. The datasheet specifica-
tions are guaranteed only for V
NONVOLATILE RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ op-
erations must be performed:
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
STORE
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
CC
goes below 4.0V. 4.0V is a
cycle time has been fulfilled,
CC
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE Cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL Cycle
= 5.0
CC
+
10%.
Sense. A