CY7C245A-35WMB Cypress Semiconductor Corp, CY7C245A-35WMB Datasheet - Page 2

• Manufacturer Part Number: CY7C245A-35WMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C245A-35WMB

• Density: 16Kb
• Organization: 2Kx8
• Access Time (max): 35ns
• Operating Current: 120mA
• Interface Type: Parallel
• Package Type: Windowed CDIP
• Operating Temperature Classification: Military
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -55C to 125C
• Pin Count: 24
• Mounting: Through Hole
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-04007 Rev. *E
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (E
asynchronous (E) output enable and asynchronous initial-
ization (INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (E
synchronous enable (E
will be in the set condition causing the outputs (O
in the OFF or high-impedance state. If the asynchronous
enable (E) is being used, the outputs will come up in the OFF
or high-impedance state only if the enable (E) input is at a
HIGH logic level. Data is read by applying the memory location
to the address inputs (A
input. The stored data is accessed and loaded into the master
flip-flops of the data register during the address set-up time. At
the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs
(O
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
If the synchronous enable (E
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to
a HIGH level. If the synchronous enable pin is switched to a
logic LOW, the subsequent positive clock edge will return the
output to the active state. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
low-to-high transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the
next location while previously addressed data remains stable
on the outputs.
System timing is simplified in that the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophis-
ticated functions such as a built-in “jump start” address. When
activated, the initialize control input causes the contents of a
user-programmed 2049th 8-bit word to be loaded into the
0
–O
7
).
S
0
) has been programmed, the register
–A
10
S
) and a logic LOW to the enable
) is being used, the outputs will
S
or E). If the
0
–O
7
) to be
S
) or
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 35 minutes. The 7C245A needs
to be within 1 inch of the lamp during erasure. Permanent
damage may result if the PROM is exposed to high-intensity
UV light for an extended period of time. 7258 Wsec/cm2 is the
recommended maximum dosage.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Bit Map Data
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
Decimal
2047
2048
2049
Programmer Address
0
.
.
.
Hex
7FF
800
801
0
.
.
.
CY7C245A
Control Byte
RAM Data
Contents
Init Byte
Data
Data
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