IPD2132 OSRAM Opto Semiconductors Inc, IPD2132 Datasheet - Page 13

• Manufacturer Part Number: IPD2132
• Description: LED Displays 5x7 Super Red 0.2 , 8-CHARACTER
• Manufacturer: OSRAM Opto Semiconductors Inc
• Series: Alphanumeric Programmable Display™r

Specifications of IPD2132

• Display Type: Dot Matrix
• Emitting Color: Hi-Eff. Red
• Number Of Digits: 8
• Digit Size (in): .2in
• Viewing Area Height (mm): 4.8mm
• Viewing Area Length (mm): 2.8mm
• Package Type: Panel
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Operating Temp Range: -55C to 100C
• Mounting: Through Hole
• Pin Count: 24
• Total Thickness (mm): 4.6mm
• Opto Display Type: Panel
• Pattern Type: Dot Matrix
• Millicandela Rating: 350µcd
• Size / Dimension: 1.68" L x 0.39" W x 0.21" H (42.7mm x 4.8mm x 5.3mm)
• Color: Red
• Configuration: 5 x 7
• Character Size: 0.2 in
• Illumination Color: High Efficiency Red
• Wavelength: 635 nm
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 55 C
• Luminous Intensity: 350 ucd
• Viewing Area (w X H): 2.8 mm x 4.8 mm
• Lead Free Status / RoHS Status: Compliant
• Voltage - Forward (vf) Typ: -
• Internal Connection: -
• Lead Free Status / Rohs Status: Details
• Other names: Q68000A8836

Clear Function (see Figure „Control Word Data Definition“
(page 13) and Table „Clear Function“ (page 13))
Control Word bit, D7 clears the character RAM to 20 hex and the
flash RAM to all zeroes. The RAMs are cleared within three clock
cycles (110 µs minimum, using the internal clock) when D7 is set
to 1. During the clear time the display must not be accessed.
When the clear function is finished, bit 7 of the Control Word RAM
will be reset to a “0”.
Control Word Data Definition
Clear Function
CE
0
0
X=don’t care
2006-04-04
D7
0
1
Function
Clear
Clear Function
Normal Operation
Clear Flash RAM & Character RAM (Character RAM = 20 Hex)
D7
WR
0
0
FL
1
1
D6
D6
0
1
Self Test
D5
X
R
A3
0
0
Self Test
Normal Operation (X = bit ignored)
Run Self Test, R = Test Result (1 = pass, 0 = fail)
D5
A2
X
X
D4
0
1
A1
X
X
Function
Blink Function
Disabled
Enabled (overrides Flash Function)
Blink
D4
A0
X
X
D3
0
1
Function
Flash
Flash Function
Disabled
Enabled
D7
0
1
D3
D6
X
X
D2
D5
X
X
13
Brightness Control
D2
0
0
0
0
1 0
1
1
1 1
Reset Function
The display should be reset on power up of the display
(RST=LOW). When the display is reset, the Character RAM, Flash
RAM, and Control Word Register are cleared.
The display's internal counters are reset. Reset cycle takes three
clock cycles (110 µs minimum using the internal clock). The dis-
play must not be accessed during this time.
To synchronize the flashing and blinking of multiple displays, it is
necessary for the display to use a common clock source and reset
all the displays at the same time to start the internal counters at
the same place.
While RST is low, the display must not be accessed by RD nor
WR.
D4
X
X
D1 D0 Brightness Control
0 0
0 1
1
1
0
1
D1
0
1
0
0 20% Brightness
0
1
D3
X
X
100% Brightness
80% Brightness
53% Brightness
40% Brightness
27% Brightness
13% Brightness
Blank Display
D0
D2
X
X
IPD2131, IPD2132, IPD2133
IDCW5161
D1
X
X
D0
X
X
Key
C
ST
BL
FL
Br
Operation
Clear disabled
Clear user RAM, flash RAM
and display
Clear Function
Self test
Blink function
Flash function
Brightness control