LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 79

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

The bit map of the Extended Parallel Port registers is:
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration
ECP IMPLEMENTATION STANDARD
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting
ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a
description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface
Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.
Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if
ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not
do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP
in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum
bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the
standard parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished
by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated.
Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware
support for compression is optional.
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
Registers.
Addr/RLE
compress
nBusy
PD7
D7
0
0
intrValue
MODE
nAck
PD6
D6
0
0
Direction
PError
PD5
D5
0
Parallel Port IRQ
Parallel Port Data FIFO
Page 79
nErrIntrEn
ackIntEn
ECP Data FIFO
Select
PD4
Test FIFO
D4
1
Address or RLE field
SelectIn
dmaEn
nFault
PD3
D3
0
serviceIntr
PD2
nInit
D2
0
0
Parallel Port DMA
autofd
PD1
D1
full
0
0
strobe
empty
PD0
D0
0
0
Note
2
1
1
2
2
2