USB2502-AEZG Standard Microsystems (SMSC), USB2502-AEZG Datasheet - Page 27

• Manufacturer Part Number: USB2502-AEZG
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB2502-AEZG

• Lead Free Status / RoHS Status: Compliant

2-Port USB 2.0 Hub Controller
Datasheet
SMSC USB2502
5.3.9.1
5.3.9.2
ADDR
NUMBER
NUMBER
REG
0Ch
0Dh
0Eh
0Fh
10h
BIT
BIT
7:3
7:0
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
Register 00h: Status/Command (Reset = 0x00)
Register 01h: Vendor ID (LSB) (Reset = 0x00)
WRITE_PROT
USB_ATTACH
Max Power (Self)
Max Power (Bus)
Hub Controller
Max Current (Self)
Hub Controller
Max Current (bus)
Power-on Time
BIT NAME
REGISTER NAME
BIT NAME
VID_LSB
Reserved
RESET
Table 5.4 SMBus Slave Interface Register Map (continued)
Least Significant Byte of the Vendor ID.
Reserved. {Note: Software must never write a ‘1’ to these bits}
Reset the SMBus Interface and internal memory back to RESET_N assertion
default settings. {Note: During this reset, this bit is automatically cleared to
its default value of 0.}
0 = Normal Run/Idle State.
1 = Force a reset.
Write Protect: The external SMBus host sets this bit after the Hub’s internal
memory is loaded with configuration data. {Note: The External SMBus Host
is responsible for verification of downloaded data.}
0 = The internal memory (address range 01-10h) is not write protected.
1 = The internal memory (address range 01-10h) is “write-protected” to
prevent unintentional data corruption.}
{Note: This bit is write once and is only cleared by assertion of the external
RESET_N pin.}
USB Attach & power-down the SMBus Interface.
0 = Default; SMBus slave interface is active.
1 = Hub will signal a USB attach event to an upstream device, Note: SMBus
Slave interface will completely power down after the ACK has completed.
{Note: This bit is write once and is only cleared by assertion of the external
RESET_N pin.}
HCMCS
HCMCB
MAXPS
MAXPB
PWRT
ABBR
DATASHEET
(MSB)
BIT 7
7
7
7
7
7
27
BIT 6
6
6
6
6
6
DESCRIPTION
DESCRIPTION
BIT 5
5
5
5
5
5
BIT 4
4
4
4
4
4
BIT 3
3
3
3
3
3
BIT 2
2
2
2
2
2
Revision 2.3 (08-27-07)
BIT 1
1
1
1
1
1
BIT 0
(LSB)
0
0
0
0
0