LPC47M112-MW Standard Microsystems (SMSC), LPC47M112-MW Datasheet - Page 24

• Manufacturer Part Number: LPC47M112-MW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M112-MW

• Lead Free Status / RoHS Status: Compliant

Enhanced Super I/O Controller with LPC Interface
Datasheet
8.5 LPC Transfer Sequence Examples
8.5.1
8.5.1.1
The LPC47M112 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110
is used for all I/O transfers. The exception to this is for transfers where IOCHRDY has been deasserted (i.e., EPP or
IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to
330 which corresponds to a timeout of 10us).
8.5.1.2
The LPC47M112 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of
0101 is used for all DMA transfers.
See the example timing for the LPC cycles in the “Timing Diagrams” section.
SMSC DS – LPC47M112
WAIT STATE REQUIREMENTS
I/O Transfers
DMA Transfers
DATASHEET
Page 24
Rev. 02-16-07