STPCI2HEYCE STMicroelectronics, STPCI2HEYCE Datasheet - Page 11

• Manufacturer Part Number: STPCI2HEYCE
• Manufacturer: STMicroelectronics

Specifications of STPCI2HEYCE

• Lead Free Status / RoHS Status: Compliant

1.7. CLOCK TREE
The STPC Atlas integrates many features and
generates all its clocks from a single 14MHz
oscillator. This results in multiple clock domains as
described in
Figure 1-2. STPC Atlas clock architecture
DEVCLK
(24MHz)
1/2
CRTC,Video,TFT
1/26
1/6
1/4
Figure
48MHz
VIP
XTALO
// Port
1-2.
UARTs
USB
14.31818 MHz
DEVCLK
VCLK
PLL
XTALI
DCLK
DCLK
PLL
OSC14M
(14MHz)
Kbd/Mouse
PCMCIA
IPC
ISA
South Bridge
MCLKO
The speed of the PLLs is either fixed (DEVCLK),
either programmable by strap option (HCLK)
either programmable by software (DCLK, MCLK).
When in synchronized mode, MCLK speed is fixed
to HCLKO speed and HCLKI is generated from
MCLKI.
1/2
ISACLK
MCLK
PWM
PLL
1/4
PCICLKI
CPU
North Bridge
MCLKI
Local Bus
HCLK
Host
PLL
SDRAM controller
1/2
1/3
GE, LDE, AFE
x2
PCICLKO
HCLKO
HCLKI
STPC® ATLAS
HCLK
11/108
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