STPCC5HEBIE STMicroelectronics, STPCC5HEBIE Datasheet - Page 6

• Manufacturer Part Number: STPCC5HEBIE
• Manufacturer: STMicroelectronics

Specifications of STPCC5HEBIE

• Operating Temperature (min): -40C
• Operating Temperature (max): 115C
• Applications: CapSense
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 2.45/3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.7/3.6V
• Package Type: BGA
• Screening Level: Industrial
• Pin Count: 388
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

GENERAL DESCRIPTION
or a 3 line flicker filter (primarily designed for
Windows type displays). The fliker filter is optional
and can be software disabled for use with large
screen area’s of video.
The Video output pipeline of the STPC Consumer-
II interfaces directly to the internal digital TV
encoder. It takes a 24 bit RGB non-interlaced pixel
stream and converts to a multiplexed 4:2:2 YCrCb
8 bit output stream, the logic includes a
progressive to interlaced scan converter and logic
to insert appropriate CCIR656 timing reference
codes into the output stream. It facilitates the high
quality display of VGA or full screen video streams
received via the Video input port to standard
NTSC or PAL televisions.
The digital PAL/NTSC encoder outputs interlaced
or non-interlaced video in PAL-B,D,G,H,I PAL-N,
PAL-M or NTSC-M standards and “NTSC- 4.43” is
also possible.
The four frame (for PAL) or 2 frame (for NTSC)
burst
subcarrier
numerically with CKREF as reference. Rise and
fall times of synchronisation tips and burst
envelope are internally controlled according to the
relevant ITU-R and SMPTE recommendations.
Video output signals are directed to four analog
output pins through internal D/A converters giving,
simultaneous
outputs.
1.4. MEMORY CONTROLLER
The STPC handles the memory data (DATA) bus
directly, controlling from 2 to 128 MBytes. The
SDRAM controller supports accesses to the
Memory Banks to/from the CPU (via the host),
from the VMI, to/from the CRTC, to the VIDEO &
to/from the GE. (Banks 0 to 3) which can be
populated with either single or double sided 72-bit
(4 bit parity) DIMMs. Parity is not supported.
The SDRAM controller only supports 64 bit wide
Memory Banks.
Four Memory Banks (if DIMMS are used; Single
sided or two double-sided DIMMs) are supported
in the following configurations (see
6/93
Bank size
Memory
1Mx64
2Mx64
4Mx64
Table 1-1. Memory configurations
sequences
generation
Number
R,G,B
16
4
8
are
and
Organisa
internally
1Mx16
2Mx8
4Mx4
tion
being
composite
Table
Release 1.5 - January 29, 2002
generated,
performed
16Mbits
Device
1-1)
Size
CVBS
The SDRAM Controller supports buffered or
unbuffered SDRAM but not EDO or FPM modes.
SDRAMs must support Full Page Mode Type
access.
The STPC Memory Controller provides various
programmable SDRAM parameters to allow the
SDRAM interface to be optimized for different
processor bus speeds SDRAM speed grades and
CAS Latency.
1.5. IDE INTERFACE
An industry standard EIDE (ATA 2) controller is
built into the STPC Consumer-II. The IDE port is
capable of supporting a total of four devices.
1.6. POWER MANAGEMENT
The STPC Consumer-II core is compliant with the
Advanced
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management
Unit
consumption providing a comprehensive set of
features that control the power usage and
supports compliance with the United States
Environmental Protection Agency's Energy Star
Computer Program. The PMU provides following
hardware structures to assist the software in
managing the power consumption by the system.
- System Activity Detection.
- Three power down timers.
- Doze timer for detecting lack of system activity
for short durations.
activity for medium durations
activity for long durations.
of house-keeping activity while dozing or in stand-
by state.
- Stand-by timer for detecting lack of system
- Suspend timer for detecting lack of system
- House-keeping activity detection.
- House-keeping timer to cope with short bursts
Bank size
Memory
16Mx64
32Mx64
16Mx64
32Mx64
4Mx64
8Mx64
4Mx64
8Mx64
Table 1-1. Memory configurations
module
Power
Number
(PMU)
16
16
16
4
8
4
8
8
Management
controls
Organisa
2Mx16x2
1Mx16x4
2Mx16x2
4Mx8x2
8Mx4x2
2Mx8x4
4Mx4x4
4Mx8x4
tion
the
128Mbits
64Mbits
Device
Size
(APM)
power