5962-9759901QZC Cypress Semiconductor Corp, 5962-9759901QZC Datasheet

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5962-9759901QZC

Manufacturer Part Number
5962-9759901QZC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of 5962-9759901QZC

# Macrocells
128
Number Of Usable Gates
3200
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
8
# I/os (max)
128
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
160
Package Type
CQFP
Memory Type
Flash
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
5962-9759901QZC
Quantity:
12
Cypress Semiconductor Corporation
Document #: 38-03029 Rev. *A
Features
Selection Guide
Maximum Propagation Delay
Minimum Set-Up, t
Maximum Clock to Output
Typical Supply Current, I
Note:
• 128 macrocells in eight logic blocks
• 128 I/O pins
• Five dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
• Fully PCI compliant
1. The 3.3V I/O mode timing adder, t
— JTAG Interface
— f
— t
— t
— t
Logic Block Diagram
MAX
PD
S
CO
= 5.5 ns
I/O
I/O
I/O
= 10 ns
= 6.5 ns
I/O
= 125 MHz
16
32
48
0
–I/O
–I/O
–I/O
–I/O
15
31
47
63
S
16 I/Os
16 I/Os
16 I/Os
16 I/Os
CC
[1]
, t
[1]
3.3IO
CO
, t
PD
, must be added to this specification when V
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
4
7C375i–125 7C375i–100 7C375i–83
64
A
B
C
D
MACROCELL
125
5.5
6.5
10
INPUT
36
16
36
16
36
16
36
16
UltraLogic™ 128-Macrocell Flash CPLD
3901 North First Street
Inputs
1
PIM
125
12
6
7
Inputs
Clock
4
36
16
36
16
36
16
36
16
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
all members of the F
designed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic™ F
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
because of the superior routability of the F
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
INPUT/CLOCK
MACROCELLS
• 3.3V or 5.0V I/O operation
• Available in 160-pin TQFP, CQFP, and PGA packages
LASH
CCIO
125
15
8
8
= 3.3V
370i™ family of high-density, high-speed CPLDs. Like
BLOCK
LOGIC
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
64
H
G
F
E
4
7C375iL–83 7C375i–66 7C375iL–66 Unit
San Jose
15
75
8
8
16 I/Os
16 I/Os
16 I/Os
16 I/Os
LASH
,
CA 95134
LASH
370i family, the CY7C375i is
I/O
I/O
I/O
I/O
125
20
10
10
370i devices, the CY7C375i
112
96
80
64
–I/O
–I/O
–I/O
–I/O
Revised May 10, 2004
111
95
79
127
LASH
EN
CY7C375i
408-943-2600
). Additionally,
20
10
10
75
370i devices,
mA
ns
ns
ns

Related parts for 5962-9759901QZC

5962-9759901QZC Summary of contents

Page 1

... Typical Supply Current Note: 1. The 3.3V I/O mode timing adder must be added to this specification when V 3.3IO Cypress Semiconductor Corporation Document #: 38-03029 Rev. *A UltraLogic™ 128-Macrocell Flash CPLD • 3.3V or 5.0V I/O operation • Available in 160-pin TQFP, CQFP, and PGA packages Functional Description ...

Page 2

Pin Configurations GND I/O /SCLK GND ...

Page 3

Pin Configurations (continued) GND I/O /SCLK GND I/O 26 ...

Page 4

Pin Configurations (continued) R I/O I/O I/O 109 112 115 P I/O I/O I/O 106 110 113 I/O 108 N I/O I/O 105 111 /SDI M I/O I/O I/O 102 104 107 L I/O I/O I/O 100 101 103 K ...

Page 5

F 370i PLDs. Note that product term allocation is LASH handled by software and is invisible to the user. I/O Macrocell Each of the macrocells on the CY7C375i has ...

Page 6

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC ...

Page 7

Inductance Parameter Description L Maximum Pin Inductance [9] Endurance Characteristics Parameter Description N Maximum Reprogramming Cycles AC Test Loads and Waveforms 238Ω (COM'L) 319Ω (MIL) 5V OUTPUT 35 pF 170Ω (COM'L) 236Ω (MIL) INCLUDING JIG AND (a) SCOPE Equivalent ...

Page 8

Switching Characteristics Over the Operating Range Parameter Description Combinatorial Mode Parameters t Input to Combinatorial Output PD t Input to Output Through Transparent Input PDL [1] or Output Latch t Input to Output Through Transparent Input PDLL [1] and Output ...

Page 9

Switching Characteristics Over the Operating Range (continued) Parameter Description Pipelined Mode Parameters t Input Register Clock to Output Register ICS Clock f Maximum Frequency in Pipelined Mode MAX4 (Least of 1/( 1 1/( ...

Page 10

Switching Waveforms (continued) Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Document #: 38-03029 Rev ...

Page 11

Switching Waveforms (continued) Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03029 Rev PDL ...

Page 12

Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 125 CY7C375i–125AC 100 CY7C375i–100AC CY7C375i–100AI 83 CY7C375i–83AC CY7C375i–83AI CY7C375i–83GMB CY7C375i–83UMB CY7C375iL–83AC Document #: 38-03029 Rev. ...

Page 13

Ordering Information (continued) Speed (MHz) Ordering Code 66 CY7C375i–66AC CY7C375i–66AI CY7C375i–66GMB CY7C375i–66UMB CY7C375iL–66AC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter ...

Page 14

Package Diagrams 160-Pin Thin Plastic Quad Flat Pack ( 1.4 mm)(TQFP) A160 Document #: 38-03029 Rev. *A CY7C375i 51-85049-*B Page ...

Page 15

Package Diagrams (continued) Document #: 38-03029 Rev. *A 160-Pin PGA G160 CY7C375i 51-80012-*A Page ...

Page 16

... Document #: 38-03029 Rev. *A © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 17

Document History Page Document Title: CY7C375i UltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03029 REV. ECN NO. Issue Date ** 106374 09/15/01 *A 213375 See ECN Document #: 38-03029 Rev. *A Orig. of Change SZV Change from Spec number: 38-00494 to ...

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