PEEL18CV8P-25L Diodes Zetex, PEEL18CV8P-25L Datasheet

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PEEL18CV8P-25L

Manufacturer Part Number
PEEL18CV8P-25L
Description
Manufacturer
Diodes Zetex
Datasheet

Specifications of PEEL18CV8P-25L

Process Technology
EECMOS
# Macrocells
8
# I/os (max)
8
Frequency (max)
33.3MHz
Propagation Delay Time
25ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
20
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEEL18CV8P-25L
Manufacturer:
ICT/AMI
Quantity:
6 960
Part Number:
PEEL18CV8P-25L
Manufacturer:
ICT/AMI
Quantity:
6 960
Part Number:
PEEL18CV8P-25L
Manufacturer:
ICT
Quantity:
5 510
Part Number:
PEEL18CV8P-25L
Manufacturer:
CN
Quantity:
5 510
Part Number:
PEEL18CV8P-25L
Manufacturer:
ICT
Quantity:
20 000
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Features
General Description
The PEEL™18CV8 is a Programmable Electrically Erasable
Logic (PEEL™) device providing an attractive alternative to
ordinary PLDs. The PEEL™18CV8 offers the performance, flex-
ibility, ease of design and production practicality needed by logic
designers today.
The PEEL™18CV8 is available in 20-pin DIP, PLCC, SOIC and
TSSOP packages with speeds ranging from 7ns to 25ns with
power consumption as low as 37mA. EE-Reprogrammability
provides the convenience of instant reprogramming for develop-
ment and reusable production inventory minimizing the impact of
programming changes or errors. EE-Reprogrammability also
improves factory testability, thus assuring the highest quality pos-
sible.
Figure 2 Pin Configuration
Multiple Speed Power, Temperature Options
CMOS Electrically Erasable Technology
Development / Programmer Support
- V
- Speeds ranging from 7ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
- Third party software and programmers
- WinPLACE Development Software
- PLD-to-PEEL™ JEDEC file translator
CC
DIP
PLCC
= 5 Volts ±10%
CMOS Programmable Electrically Erasable Logic Device
I/CLK
TSSOP
GND
SOIC
I
I
I
I
I
I
I
I
contact factory for availability
10
2
3
4
5
6
7
8
9
PEEL™ 18CV8 -7/-10/-15/-25
1
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
1/9
The PEEL™18CV8 architecture allows it to replace over 20 stan-
dard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides addi-
tional architecture features so more logic can be put into every
design. Anachip’s JEDEC file translator instantly converts to the
PEEL™18CV8 existing 20-pin PLDs without the need to rework
the existing design. Development and programming support for the
PEEL™18CV8 is provided by popular third-party program- mers
and development software.
Figure 3 Block Diagram
Architectural Flexibility
Application Versatility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
- 20 Pin DIP/SOIC/TSSOP and PLCC
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary PLDs
Rev. 1.0 Dec 16, 2004

Related parts for PEEL18CV8P-25L

PEEL18CV8P-25L Summary of contents

Page 1

CMOS Programmable Electrically Erasable Logic Device Features Multiple Speed Power, Temperature Options - Volts ±10 Speeds ranging from 7ns Power as low as 37mA at 25MHz - ...

Page 2

Figure 4 PEEL™18CV8 Logic Array Diagram Anachip Corp. www.anachip.com.tw 2/9 Rev. 1.0 Dec 16, 2004 ...

Page 3

Function Description The PEEL™18CV8 implements logic functions as sum-of- prod- ucts expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connec- tions of input signals into the array. User-configurable output structures in ...

Page 4

I/O will function as a dedicated input. Input/Feedback Select The PEEL™18CV8 macrocell also provides control over the feedback path. The input/feedback signal associated with each I/ O macrocell may be ...

Page 5

Figure 4 Equivalent Circuits for the Twelve Configurations of the PEEL™18CV8 I/O Macrocell Anachip Corp. www.anachip.com.tw 5/9 Rev. 1.0 Dec 16, 2004 ...

Page 6

Absolute Maximum Ratings Operating Range D.C. Electrical Characteristics Over the operating range (Unless otherwise specified) Anachip Corp. www.anachip.com.tw This device has been designed and tested for the specified operat- ing ranges. Improper operation outside of these ...

Page 7

A.C. Electrical Characteristics 8 Over the operating range Switching Waveforms Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs Notes: 1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V ...

Page 8

... PEEL18CV8JI-10 (L) PEEL18CV8S-10 ( PEEL18CV8SI-10 (L) PEEL18CV8T-10 ( PEEL18CV8TI-10 (L) PEEL18CV8P-15 ( PEEL18CV8PI-15 (L) PEEL18CV8J-15 ( PEEL18CV8JI-15 (L) PEEL18CV8S-15 ( PEEL18CV8SI-15 (L) PEEL18CV8T-15 (L) 15ns PEEL18CV8TI-15 (L) PEEL18CV8P-25 ( PEEL18CV8PI-25 (L) PEEL18CV8J-25 ( PEEL18CV8JI-25 (L) PEEL18CV8S-25 ( PEEL18CV8SI-25 (L) PEEL18CV8T-25 ( PEEL18CV8TI-25 (L) Anachip Corp. www.anachip.com.tw Temperature Commercial 20-pin Plastic 300 mil DIP Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC) Commercial ...

Page 9

Part Number Package P = 20-pin Plastic 300mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170mil Anachip Corp. Head Office, 2F, No. ...

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