54ABT373J-QML National Semiconductor, 54ABT373J-QML Datasheet

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54ABT373J-QML

Manufacturer Part Number
54ABT373J-QML
Description
Manufacturer
National Semiconductor
Type
D-Typer
Datasheet

Specifications of 54ABT373J-QML

Logic Family
ABT
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
BiCMOS
Package Type
CDIP
Propagation Delay Time
8ns
Operating Supply Voltage (typ)
5V
High Level Output Current
-24mA
Low Level Output Current
48mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Through Hole
Pin Count
20
Output Type
3-State
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
54ABT373J-QML 5962-9321801QRA
Manufacturer:
S
Quantity:
2
© 1998 National Semiconductor Corporation
54ABT373
Octal Transparent Latch with TRI-STATE
General Description
The ’ABT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state.
Features
n TRI-STATE outputs for bus interfacing
n Output sink capability of 48 mA, source capability of
Ordering Code
Connection Diagrams
TRI-STATE
54ABT373J-QML
54ABT373W-QML
54ABT373E-QML
24 mA
®
is a registered trademark of National Semiconductor Corporation.
Military
for DIP and Flatpak
Pin Assignment
DS100206
Package Number
DS100206-1
W20A
E20A
J20A
D
LE
OE
O
Pin Names
0
0
–D
–O
7
7
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch
(Active HIGH)
(Active LOW)
Outputs
Description
n Guaranteed multiple output switching specifications
n Output switching specified for both 50 pF and 250 pF
n Guaranteed simultaneous switching, noise level and
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9321801
loads
dynamic threshold performance
power up and power down
Package Description
Pin Assignment
®
for LCC
Outputs
DS100206-2
www.national.com
July 1998

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54ABT373J-QML Summary of contents

Page 1

... LOW. When OE is HIGH the bus output is in the high impedance state. Features n TRI-STATE outputs for bus interfacing n Output sink capability of 48 mA, source capability Ordering Code Military Package Number 54ABT373J-QML J20A 54ABT373W-QML W20A 54ABT373E-QML E20A Connection Diagrams Pin Assignment for DIP and Flatpak ...

Page 2

Functional Description The ’ABT373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this condition the n latches are transparent, i.e., a latch output ...

Page 3

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 2) ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH PHL Propagation Delay PLH PHL n t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ...

Page 5

Capacitance (Continued Temperature (T ) PZH pF, 1 Output Switching Output t vs Temperature (T ) PHZ pF, 1 Output Switching Output t LOW ...

Page 6

Capacitance (Continued) t HIGH vs Temperature (T HOLD = 50 pF, 1 Output Switching C L Data Temperature (T PLH = 50 pF, 8 Outputs Switching C L Data to Output t vs Temperature (T PZH ...

Page 7

Capacitance (Continued Temperature (T ) PHZ pF, 8 Outputs Switching Output t vs Load Capacitance PLH = 25˚C, 1 Output Switching T A Data to Output t vs Load Capacitance PLH ...

Page 8

Capacitance (Continued Load Capacitance PZH = 25˚C, 8 Outputs Switching Output t vs Temperature (T PLH = 50 pF, 1 Output Switching Output t vs Temperature (T PLH = 50 ...

Page 9

Capacitance (Continued) t and t vs Number Outputs Switching PLH PHL = 50 pF 25˚ 5.0V Outputs In Phase Data to Output Dashed lines represent design characteristics; for specified guarantees, refer to ...

Page 10

AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate t w 3.0V 1 MHz 500 ns FIGURE 3. Test Input Signal Requirements FIGURE 4. Propagation Delay Waveforms ...

Page 11

11 ...

Page 12

Physical Dimensions inches (millimeters) unless otherwise noted www.national.com 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A 12 ...

Page 13

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 20-Lead Ceramic Flatpak (F) NS Package Number W20A 13 www.national.com ...

Page 14

... National Semiconductor Asia Pacific Customer Fax: +49 (0) 1 80-530 85 86 Response Group Email: europe.support@nsc.com Tel: 65-2544466 Fax: 65-2504466 Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Tel: +49 (0) 1 80-534 16 80 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 ...

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