LT330-BD-0239A ARM, LT330-BD-0239A Datasheet - Page 2

• Manufacturer Part Number: LT330-BD-0239A
• Manufacturer: ARM

Specifications of LT330-BD-0239A

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Specification
Logic Tile Features
 Virtex-5 XC5VLX330 FPGA
 2 JTAG scan-chains for debug and FPGA programming
 Configuration Flash to store 2 FPGA images
 8 User switches
 8 User LEDs
 3 programmable clock generators
 Push button
 Battery for FPGA encryption key
 On-board 32MB ZBT SRAM
Comparison with Virtex-4 Logic Tiles
Ordering Information
ARM, ARM Powered, StrongARM, Thumb, Multi-ICE, PrimeCell, RealView, ARM7TDMI, ARM9TDMI, EmbeddedICE and Jazelle are registered trademarks of ARM Limited. ARM7TDMI- S, ARM7EJ-S, ARM720T, ARM920T, ARM922T, ARM9E, ARM926EJ - S, ARM946E-S, ARM966E-S, ARM1020E, ARM1022E, ARM1026EJ-S, ARM11, ARM1136J -S,
ARM1136JF-S, ETK11, ETM, ETM7, ETM9, ETM10, ETM10RV, ETM11RV, ETB11, ETB, EmbeddedICE -RT, AMBA, ModelGen, ARM Developer Suite, Embedded Trace Macrocell, PrimeXsys, MOVE, Integrator, and JTEK are trademarks of ARM Limited. Java is a trademark of Sun Microsystems, Inc. XScale is a trademark of Intel Corporation. All other
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document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. All warranties implied or expressed,
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LT-XC5VLX330+_Datasheet v2.doc
Example system: Core Tile for ARM11 MPCore, Emulation Baseboard and Logic Tiles
Feature
FPGA slices
Header I/O pins
External clock signals
ZBT SRAM
FPGA block RAM
User LEDs and switches
Header I/O fold switches
Part number
LT330-BD-0239A
Description
Logic Tile for XC5VLX330
0.65MB / 0.7MB
Upper and lower
LT-XC4VLX160
LT-XC4VLX200
68K / 89K
918
21
8
-
Upper and lower
LT-XC5VLX330
1.3MB
32MB
331K
918
21
8
Deliverables
I/O signals on stacking connectors
The stacking connectors and I/O connections
are a superset of the Virtex-II and Virtex-4
Logic Tiles.
On-board switches can be configured to
connect signals from the FPGA to these pins
or to route signals straight through the board
 Documentation
 Example RTL and FPGA bit-files for a Logic
Tile on top of a RealView Platform Baseboard
or Emulation Baseboard
 Utility to reprogram the FPGA configuration
Flash with RealView ICE or the USB debugger
integrated on RealView baseboards
HDRX
HDRY
HDRZ
HDRZ through
Header
Distributor
Top
144
144
107
128
Bottom
144
144
107