LT4256-3CGNTR Linear Technology, LT4256-3CGNTR Datasheet - Page 14

• Manufacturer Part Number: LT4256-3CGNTR
• Manufacturer: Linear Technology

Specifications of LT4256-3CGNTR

• Family Name: LT4256-3
• Package Type: SSOP N
• Operating Supply Voltage (min): 10.8V
• Operating Supply Voltage (max): 80V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

APPLICATIO S I FOR ATIO
LT4256-3
Therefore, using RETRY only, the LT4256-3 will either
latch off after an overcurrent fault condition or it will go
into a hiccup mode.
Power Good Detection
The LT4256-3 includes a comparator for monitoring the
output voltage. The output voltage is sensed through the
FB pin via an external resistor string. The comparator’s
output (PWRGD) is an open collector capable of operating
from a pull-up as high as 80V.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by tran-
sistor Q2 and R10.
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
14
U
GND
24V
V
CC
U
0.01µF
(SHORT PIN)
C3
W
Figure 12. Active Low Enable PWRGD Application
R1
32.4k
R2
4.02k
R3
4.02k
C2
33nF
D2
SMAT70A
1
2
4
9
UV
OV
OPEN
TIMER
U
V
CC
LT4256-3
16
100mΩ
GND
R5
8
SENSE
PWRGD
RETRY
GATE
V
15
OUT
FB
13
12
10
7
5
OPEN Pin/Open FET Detection
OPEN is an output which signals abnormally low load
currents. When the voltage across the sense resistor is
less than 3mV, the open collector pull-down device is shut
off allowing OPEN to be externally pulled high. OPEN is
always active when V
(the internal UVLO threshold), OPEN is pulled low.
Open-circuit MOSFETs are detected with the LT4256-3 by
monitoring the voltage across R5 with OPEN while moni-
toring the output voltage with PWRGD. An open FET
condition is signalled when OPEN is high and PWRGD is
low (after the part has completed its start-up cycle).
IRFZ34VS
R
20
V
UV = 20V
OV = 40V
PWRGD = 18V
Q1
THPWRGD
8 =
R7
100Ω
R9
4.02k
R6
10Ω
k
C1
10nF
Ω ≤
⎛
⎜
⎝
V
D1
CMPZ5241BS
11V
THPWRGD
R
3 99
8
14k
.
R8
= 4.45V 1+
+
27k
R4
V
R
9 200
≤
CC
–
⎛
⎜
⎝
1
is above 9.8V. If V
⎞
⎟
⎠
Q2
ZN3904
R10
51k
4256 F12
+
• R9, high to low
k
R8
R9
PWRGD
Ω
C
L
⎞
⎟
⎠
V
24V
400mA
V
, low to high
OUT
LOGIC
CC
is below 9.8V
42563fa
(8b)
(8a)
(7)